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MC33341 Datasheet(PDF) 7 Page - ON Semiconductor |
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MC33341 Datasheet(HTML) 7 Page - ON Semiconductor |
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7 / 19 page ![]() MC33341 http://onsemi.com 7 Pin 8 to ground. This configuration is shown for ease of understanding and would normally be used to provide an isolated control signal to a primary side switching regulator controller. In non−isolated, primary or secondary side applications, a load resistor can be placed from Pin 8 to ground. This resistor will convert the Drive Output current to a voltage for direct control of a regulator. In applications where excessively high peak currents are possible from the source or load, the load induced voltage drop across RS could exceed 1.6 V. Depending upon the current sensing configuration used, this will result in forward biasing of either the internal VCC clamp diode, Pin 6, or the device substrate, Pin 1. Under these conditions, input series resistor R3 is required. The peak input current should be limited to 20 mA. Excessively large values for R3 will degrade the current sensing accuracy. Figure 22 shows a method of bounding the voltage drop across RS without sacrificing current sensing accuracy. Figure 14. Source High−Side Current Sensing with Internally Fixed Voltage and Current Thresholds RS Load R1 Battery or Resistive Load Source Return Source R2 R3 Comp The above figure shows the MC33341 configured for source high−side current sensing allowing a common ground path between Load − and Source Return −. The Differential Amplifier inputs, Pins 1 and 6, are used to sense the load induced voltage drop that appears across resistor RS. The internal voltage and current regulation thresholds are selected by the respective external connections of Pins 2 and 6. Resistor R3 is required in applications where a high peak level of reverse current is possible if the source inputs are shorted. The resistor value should be chosen to limit the input current of the internal VCC clamp diode to less than 20 mA. Excessively large values for R3 will degrade the current sensing accuracy. Vreg + Vth(V) R2 R1 ) 1 + 1.2 R2 R1 ) 1 Ireg + V th(IHS) R S + 0.2 R S R3 + I pk R S – 0.6 0.02 V I Load 87 6 5 12 3 4 R R R R R VCC VCC VCC VCC VCC VCC 0.4 V 1.2 V R 0.2 V VCC 0.2 V 0.4 V 1.2 V VCC 1.2 V VCC Inverting Amp Transconductance Amp Differential Amp Disable Logic Differential Amp Opto Isolator Vsen Vth Isen Ith Reference |
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