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AT83SND2CMP3B Datasheet(PDF) 86 Page - ATMEL Corporation |
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AT83SND2CMP3B Datasheet(HTML) 86 Page - ATMEL Corporation |
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86 / 241 page  86 4341F–MP3–03/06 AT8xC51SND2C/MP3B Table 15-1. Dac SPI Interface Timings 15.1.5 DAC Register Tables Table 15-2. DAC Register Address 15.1.6 DAC Gain The DAC implements severals gain control: line-in (Table 15-3.), master playback (), line-out (Table 15-6.). Timing parameter Description Min Max Tc AUDCCLK min period 150 ns - Twl AUDCCLK min pulse width low 50 ns - Twh AUDCCLK min pulse width high 50 ns - Tssen Setup time AUDCCS falling to AUDCCLK rising 50 ns - Thsen Hold time AUDCCLK falling to AUDCCS rising 50 ns - Tssdi Setup time AUDCDIN valid to AUDCCLK falling 20 ns - Thsdi Hold time AUDCCLK falling to AUDCDIN not valid 20 ns - Tdsdo Delay time AUDCCLK rising to AUDCDOUT valid - 20 ns Thsdo Hold time AUDCCLK rising to AUDCDOUT not valid 0 ns - Address Register Name Access Reset state 00h DAC_CTRL Dac Control Read/Write 00h 01h DAC_LLIG Dac Left Line in Gain Read/Write 05h 02h DAC_RLIG Dac Right Line in Gain Read/Write 05h 03h DAC_LPMG Dac Left Master Playback Gain Read/Write 08h 04h DAC_RPMG Dac Right Master Playback Gain Read/Write 08h 05h DAC_LLOG Dac Left Line Out Gain Read/Write 00h 06h DAC_RLOG Dac Right Line Out Gain Read/Write 00h 07h DAC_OLC Dac Output Level Control Read/Write 22h 08h DAC_MC Dac Mixer Control Read/Write 09h 09h DAC_CSFC Dac Clock and Sampling Frequency Control Read/Write 00h 0Ah DAC_MISC Dac Miscellaneous Read/Write 00h 0Ch DAC_PRECH Dac Precharge Control Read/Write 00h 0Dh DAC_AUXG Dac Auxilary input gain Control Read/Write 05h 10h DAC_RST Dac Reset Read/Write 00h 11h PA_CRTL Power Amplifier Control Read/Write 00h |
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