AT83SND2CMP3B datasheet(110/241 Pages) ATMEL

110 / 241 page

110

4341F–MP3–03/06

AT8xC51SND2C/MP3B

16.6

Bulk/Interrupt Transactions

Bulk and Interrupt transactions are managed in the same way.

16.6.1

Bulk/Interrupt OUT Transactions in Standard Mode

Figure 16-9.

Bulk/Interrupt OUT transactions in Standard Mode

An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt

packets.

When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB con-

troller. This triggers an interrupt if enabled. The firmware has to select the corresponding

endpoint, store the number of data Bytes by reading the UBYCTX register. If the received packet

is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be

read.

When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUTB0 bit

to allow the USB controller to accept the next OUT packet on this endpoint. Until the RXOUTB0

bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each

OUT requests.

If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be

stored, but the USB controller will consider that the packet is valid if the CRC is correct and the

endpoint Byte counter contains the number of Bytes sent by the Host.

OUT

DATA0 (n Bytes)

ACK

HOST

UFI

C51

Endpoint FIFO Read Byte 1

OUT

DATA1

NAK

RXOUTB0

Endpoint FIFO Read Byte 2

Endpoint FIFO Read Byte n

Clear RXOUTB0

OUT

DATA1

NAK

OUT

DATA1

ACK

RXOUTB0

Endpoint FIFO Read Byte 1

AT83SND2CMP3B Datasheet(PDF) 110 Page - ATMEL Corporation

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