AD8315ARMZ datasheet(17/24 Pages) AD

17 / 24 page

AD8315

Rev. C | Page 17 of 24

In a power control loop, the AD8315 provides both the detector

and controller functions. A sample of the power amplifier’s (PA)

output power is coupled to the RF input of the AD8315, usually

via a directional coupler. In dual-mode applications, where

there are two PAs and two directional couplers, the outputs of

the directional couplers can be passively combined (both PAs

will never be turned on simultaneously) before being applied to

the AD8315.

A setpoint voltage is applied to VSET from the controlling

source (generally, this is a DAC). Any imbalance between the

RF input level and the level corresponding to the setpoint

voltage is corrected by the AD8315’s VAPC output that drives

the gain control terminal of the PA. This restores a balance

between the actual power level sensed at the input of the

AD8315 and the value determined by the setpoint. This

assumes that the gain control sense of the variable gain

element is positive, that is, an increasing voltage from

VAPC tends to increase gain.

VAPC can swing from 250 mV to within 100 mV of the supply

rail and can source up to 6 mA. If the control input of the PA

needs to source current, a suitable load resistor can be connected

between VAPC and COMM. The output swing and current

sourcing capability of VAPC is shown in Figure 21.

RANGE ON VSET AND RFIN

The relationship between the RF input level and the setpoint

voltage follows from the nominal transfer function of the device

(see Figure 4, Figure 5, Figure 7, and Figure 8). At 0.9 GHz, for

example, a voltage of 1 V on VSET indicates a demand for

−30 dBV (−17 dBm, re 50 Ω) at RFIN. The corresponding power

level at the output of the power amplifier is greater than this

amount due to the attenuation through the directional coupler.

For setpoint voltages of less than approximately 250 mV, VAPC

remains unconditionally at its minimum level of approximately

250 mV. This feature can be used to prevent any spurious

emissions during power-up and power-down phases.

Above 250 mV, VSET has a linear control range up to 1.4 V,

corresponding to a dynamic range of 50 dB. This results in a

slope of 23 mV/dB or approximately 43.5 dB/V.

TRANSIENT RESPONSE

The time domain response of power amplifier control loops,

using any kind of controller, is only partially determined by the

choice of filter, which, in the case of the AD8315, has a true

integrator form 1/sT, as shown in Equation 7, with a time

constant given by Equation 8. The large signal step response is

also strongly dependent on the form of the gain-control law.

Nevertheless, some simple rules can be applied. When the filter

capacitor CFLT is very large, it dominates the time domain

response, but the incremental bandwidth of this loop still varies

as VAPC traverses the nonlinear gain-control function of the PA,

as shown in Figure 35. This bandwidth is highest at the point

where the slope of the tangent drawn on this curve is greatest,

that is, for power outputs near the center of the PA’s range, and

is much reduced at both the minimum and the maximum

power levels, where the slope of the gain control curve is lowest

due to its S-shaped form.

Using smaller values of CFLT, the loop bandwidth generally

increases in inverse proportion to its value. Eventually, however,

a secondary effect appears due to the inherent phase lag in the

power amplifier’s control path, some of which can be due to

parasitic or deliberately added capacitance at the VAPC pin.

This results in the characteristic poles in the ac loop equation

moving off the real axis and thus becoming complex (and

somewhat resonant). This is a classic aspect of control loop

design. The lowest permissible value of CFLT needs to be determined

experimentally for a particular amplifier. For GSM and DCS

power amplifiers, CFLT typically ranges from 150 pF to 300 pF.

In many cases, some improvement in the worst-case response

time can be achieved by including a small resistance in series

with CFLT; this generates an additional 0 in the closed-loop

transfer function, that serves to cancel some of the higher order

poles in the overall loop. A combination of main capacitor CFLT

shunted by a second capacitor and resistor in series is also

useful in minimizing the settling time of the loop.

AD8315ARMZ Datasheet(PDF) 17 Page - Analog Devices

AD8315ARMZ Datasheet(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL