AD8315ARMZ datasheet(18/24 Pages) AD

18 / 24 page

AD8315

Rev. C | Page 18 of 24

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMM

FLTR

ENABLE

0V/2.7V

LDC15D190A0007A

ATTN

20dB

PF08107B

VCTL

VAPC

1000pF

3.5V

1000pF

0.1µF

1.5kΩ

150pF

52.3Ω

49.9Ω

4.7µF

500Ω

AD8315

BAND

SELECT

0V/2V

POUT GSM

35dBm MAX

POUT DCS

32dBm MAX

PIN GSM

3dBm

PIN DCS

3dBm

(OPTIONAL,

SEE TEXT)

+VS

2.7V

R31

1kΩ

R21

600Ω

1R2, R3 OPTIONAL,

SEE TEXT

8-BIT

RAMP DAC

0V TO 2.55V

ANTENNA

Figure 38. Dual-Mode (GSM/DCS) PA Control Example

MOBILE HANDSET POWER CONTROL EXAMPLE

Figure 38 shows a complete power amplifier control circuit for a

dual-mode handset. The PF08107B (Hitachi), a dual mode

(GSM, DCS) PA, is driven by a nominal power level of 3 dBm.

The PA has a single gain control line; the band to be used is

selected by applying either 0 V or 2 V to the PA’s VCTL input.

Some of the output power from the PA is coupled off using a

dual-band directional coupler (Murata LDC15D190A0007A).

This has a coupling factor of approximately 19 dB for the GSM

band and 14 dB for DCS and an insertion loss of 0.38 dB and

0.45 dB, respectively. Because the PF08107B transmits a maximum

power level of 35 dBm for GSM and 32 dBm for DCS, additional

attenuation of 20 dB is required before the coupled signal is

applied to the AD8315. This results in peak input levels to the

AD8315 of −4 dBm (GSM) and −2 dBm (DCS). While the

AD8315 gives a linear response for input levels up to 2 dBm,

for highly temperature-stable performance at maximum PA

output power, the maximum input level should be limited to

approximately −2 dBm (see Figure 5 and Figure 7). This does,

however, reduce the sensitivity of the circuit at the low end.

The operational setpoint voltage, in the range 250 mV to 1.4 V,

is applied to the VSET pin of the AD8315. This is typically

supplied by a DAC. The AD8315’s VAPC output drives the

level control pin of the power amplifier directly. VAPC reaches a

maximum value of approximately 2.5 V on a 2.7 V supply while

delivering the 3 mA required by the level control input of the

PA. This is more than sufficient to exercise the gain control

range of the PA.

During initialization and completion of the transmit sequence,

VAPC should be held at its minimum level of 250 mV by keeping

VSET below 200 mV.

In this example, VSET is supplied by an 8-bit DAC that has an

output range from 0 V to 2.55 V or 10 mV per bit. This sets the

control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times

10 mV). If finer resolution is required, the DAC’s output voltage

can be scaled using two resistors, as shown in Figure 38. This

converts the DAC’s maximum voltage of 2.55 V down to 1.6 V

and increases the control resolution to 0.25 dB/bit.

A filter capacitor (CFLT) must be used to stabilize the loop. The

choice of CFLT depends to a large degree on the gain control

dynamics of the power amplifier, something that is frequently

poorly characterized, so some trial and error can be necessary.

In this example, a 150 pF capacitor is used and a 1.5 kΩ series

resistor is included. This adds a zero to the control loop and

AD8315ARMZ Datasheet(PDF) 18 Page - Analog Devices

AD8315ARMZ Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL