AT43USB325E-AC datasheet(26/109 Pages) ATMEL

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3355C–USB–4/05

AT43USB325

4.9

Non-USB Related Interrupt Handling

The AT43USB325 has two non-USB 8-bit Interrupt Mask control registers; GIMSK (General

Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register).

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are

disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set

(one) when a Return from Interrupt instruction, RETI, is executed.

For Interrupts triggered by events that can remain static (e.g. the Output Compare register1

matching the value of Timer/Counter1) the interrupt flag is set when the event occurs. If the

interrupt flag is cleared and the interrupt condition persists, the flag will not be set until the event

occurs the next time.

When the Program Counter is vectored to the actual interrupt vector in order to execute the

interrupt handling routine, hard-ware clears the corresponding flag that generated the interrupt.

Some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to

be cleared.

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the

interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by

software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero),

the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable

bit is set (one), and will be executed by order of priority.

Note that external level interrupt does not have a flag, and will only be remembered for as long

as the interrupt condition is active.

4.9.1

General Interrupt Mask Register – GIMSK

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU

general Control Register (MCUCR) defines whether the external interrupt is activated on rising

or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request

even if INT1 is configured as an output. The corresponding interrupt of External Interrupt

Request 1 is executed from program memory address $004. See also “External Interrupts” on

page 29.

• Bit 6 – INT0: Interrupt Request 0 (Suspend/Resume Interrupt) Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU

general Control Register (MCUCR) defines whether the external interrupt is activated on rising

or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request

even if INT0 is configured as an output. The corresponding interrupt of Interrupt Request 0 is

executed from program memory address $002. See also “External Interrupts” on page 29.

Bit

210

$3B ($5B)

INT1

INT0

–

GIMSK

Read/Write

R/W

Initial Value

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