1999 November

14

Philips Semiconductors

Product specification

Full Frame CCD Image Sensor

FTF3020-C

Pin configuration

The FTF3020-C is mounted in a Pin Grid Array (PGA) package with

(quadrant W) is marked with a gold dot on top of the package.

Figure 12 - FTF3020-C pin configuration (top view)

The image clock phases of quadrant W are internally connected to

X, and Y is connected to Z.

Symbol

Name

Pin # W

Pin # X

Pin # Y

Pin # Z

VNS

VNS

VNS

VNS

VPS

SFD

SFS

VCS

OG

RD

A1

A2

A3

A4

C1

C2

C3

SG

RG

OUT

NC

NC

NC

NC

N substrate

N substrate

N substrate

N substrate

P substrate

Source Follower Drain

Source Follower Source

Current Source

Output Gate

Reset Drain

Image Clock (Phase 1)

Image Clock (Phase 2)

Image Clock (Phase 3)

Image Clock (Phase 4)

Register Clock (Phase 1)

Register Clock (Phase 2)

Register Clock (Phase 3)

Summing Gate

Reset Gate

Output

Not Connected

Not Connected

Not Connected

Not Connected

A1

A5

C2

G1

A2

B2

D2

C1

B3

D1

B5

A3

A4

B4

F2

F1

G2

E1

E2

B1

I1

I2

H1

H2

U1

U5

S2

M1

U2

T2

R2

S1

T3

R1

T5

U3

U4

T4

N2

N1

M2

P1

P2

T1

K1

K2

L1

L2

U10

U6

S9

M10

U9

T9

R9

S10

T8

R10

T6

U8

U7

T7

N9

N10

M9

E10

P9

T10

K10

K9

L10

L9

A10

A6

C9

G10

A9

B9

D9

C10

B8

D10

B6

A8

A7

B7

F9

F10

G9

P10

E9

B10

I10

I9

H10

H9

AB

C

D

E

F

G

H

J

KL

M

N

P

R

S

T

U

10

9

8

7

6

5

4

3

2

1

TOP

Y

Z

X

W

FTF3020-C