CS8405A

30

DS469F2

OMCK

21 Master Clock (Input) - The frequency must be only 256x the sample rate.

ISCLK

13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.

ILRCK

12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the

SDIN pin.

SDIN

14 Serial Audio Data Port (Input) - Audio data serial input pin.

SFMT0

SFMT1

4

5

Serial Audio Data Format Select

(Input) - Selecta the serial audio input port format. See Table 3.

APMS

10 Serial Audio Data Port Master/Slave Select (Input) - APMS should be connected to VL+ to set

serial audio input port as a master or connected to DGND to set the port as a slave.

TCBLD

11 Transmit Channel Status Block Direction (Input) - Connect TCBLD to VL+ to set TCBL as an out-

put. Connect TCBLD to DGND to set TCBL as an input.

TCBL

15 Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high dur-

ing the first sub-frame of a transmitted channel status block, and low at all other times. When oper-

ated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-

frame to be the start of a channel status block.

CEN

16 C Bit Enable (Input) - Determines how the channel status data bits are input. When CEN is low,

hardware mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter

selected channel status data. When CEN is high, hardware mode B is selected, where the COPY/C

pin is used to enter serial channel status data.

V

17 Validity Bit (Input) - In hardware modes A and B, the V pin input determines the state of the validity

bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.

U

18 User Data Bit (Input) - In hardware modes A and B, the U pin input determines the state of the user

data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.

COPY/C

1 COPY Channel Status Bit/C Bit (Input) - In hardware mode A (CEN = 0), the COPY/C and ORIG

pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data

stream, see Table 2. In hardware mode B, the COPY/C pin becomes the direct C bit input data pin.

EMPH

3 Pre-Emphasis Indicator (Input) - In hardware mode A (CEN = 0), the EMPH pin low sets the 3

emphasis channel status bits to indicate 50/15 ms pre-emphasis of the transmitted audio data. If

EMPH is high, then the three EMPH channel status bits are set to 000, indicating no pre-emphasis.

AUDIO

19 Audio Channel Status Bit (Input) - In hardware mode A (CEN = 0), the AUDIO pin determines the

state of the audio/non audio Channel Status bit in the outgoing AES3 data stream.

ORIG

28 ORIG Channel Status Bit Control (Input) - In hardware mode A (CEN = 0), the ORIG and COPY/C

pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data

stream, see Table 2.