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TDP2004 Datasheet(PDF) 8 Page - Texas Instruments |
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TDP2004 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 29 page  5.6 High Speed Electrical Characteristics over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Receiver RLRX-DIFF Input differential return loss 3 GHz -19 dB 4 GHz -18 dB 5 GHz -18 dB 6 GHz -17 dB 10 GHz -15 dB XTRX Receiver-side pair-to-pair isolation; Port A or Port B Minimum over 10 MHz to 10 GHz range -60 dB Transmitter RLTX-DIFF Output differential return loss 3 GHz -19 dB RLTX-DIFF Output differential return loss 4.0 GHz -18 dB RLTX-DIFF Output differential return loss 5.0 GHz -18 dB RLTX-DIFF Output differential return loss 6.0 GHz -17 dB RLTX-DIFF Output differential return loss 10 GHz -16 dB XTTX Transmit-side pair-to-pair isolation Minimum over 10 MHz to 10 GHz range -60 dB Device Datapath TPLHD/PHLD Input-to-output latency (propagation delay) through a data channel For either low-to-high or high-to-low transition. 100 130 ps LTX-SKEW Lane-to-lane output skew Between any two lanes within a single transmitter. 20 ps TRJ-DATA Additive random jitter with data Jitter through redriver minus the calibration trace. 20Gbps PRBS15. 800 mVpp-diff input swing 70 fs XT Channel to channel xtalk (between adjacent active channels, FEXT Minimum over 10 MHz to 10 GHz range, normalized to EQ gain of 0dB -43 dB FLAT-GAIN Broadband DC and AC flat gain - input to output, measured at DC Minimum EQ, GAIN = L0 -5.6 dB Minimum EQ, GAIN = L1 -3.8 dB Minimum EQ, GAIN = L2 -1.2 dB Minimum EQ, GAIN = L3 2.6 dB Minimum EQ, GAIN = L4 (Float) 0.6 dB EQ-MAX10G EQ boost at max setting (EQ INDEX = 19) AC gain at 10 GHz relative to gain at 100 MHz. 19 dB LINEARITY- DC Output DC linearity at GAIN = L4 1750 mVpp LINEARITY- AC Output AC linearity at 10Gbps, with GAIN = L4 1100 mVpp at 20Gbps, with GAIN = L4 1080 mVpp 5.7 SMBUS/I2C Timing Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Secondary Mode tSP Pulse width of spikes which must be suppressed by the input filter 50 ns tHD-STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs TDP2004 SNLS745 – NOVEMBER 2023 www.ti.com 8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDP2004 |
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