6.4 Device Functional Modes

6.4.1 Active Mode

The device is in normal operation. In this mode, the TDP2004 redrives and equalizes video mainlink signals to

provide better signal integrity.

6.4.2 Standby Mode

The device is in standby mode invoked by PD = H. In this mode, the device is in standby mode conserving

power.

6.5 Programming

6.5.1 Pin mode

The TDP2004 can be fully configured through pin-strap pins. In this mode the device uses 2-level and 5-level

pins for device control and signal integrity optimum settings.

6.5.1.1 Five-Level Control Inputs

The TDP2004 has four (EQ0, EQ1, GAIN, and MODE) 5-level input pins that are used to control the

configuration of the device. These 5-level inputs use a resistor divider to help set the 5 valid levels and provide

a wider range of control settings. External resistors must be of 10% tolerance or better. The 5-level pins except

MODE are sampled at power-up only. The MODE pin can be exercised at device power up or in normal

operation mode.

Table 6-3. 5-level Control Pin Settings

LEVEL

SETTING

L0

1 kΩ to GND

L1

8.25 kΩ to GND

L2

24.9 kΩ to GND

L3

75 kΩ to GND

L4

F (Float)

6.5.2 SMBUS/I2C Register Control Interface

If MODE = L2 (SMBus/I2C Secondary control mode), then the TDP2004 is configured through a standard I2C

or SMBus interface that may operate up to 400 kHz. The secondary address of the TDP2004 is determined by

the pin strap settings on the ADDR1 and ADDR0 pins. The sixteen possible secondary addresses for channels

0-3 are provided in Table 6-4. In SMBus/I2C modes the SCL and SDA pins must be pulled up to a 3.3 V

supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩ is a good first

approximation for a bus capacitance of 10 pF.

Table 6-4. SMBUS/I2C Secondary Address Settings

ADDR1

ADDR0

7-bit Secondary Address Channels 0-3

L0

L0

0x18

L0

L1

0x1A

L0

L2

0x1C

L0

L3

0x1E

L0

L4

Reserved

L1

L0

0x20

L1

L1

0x22

L1

L2

0x24

L1

L3

0x26

L1

L4

Reserved

L2

L0

0x28

L2

L1

0x2A

www.ti.com

TDP2004

SNLS745 – NOVEMBER 2023

Copyright © 2023 Texas Instruments Incorporated

Submit Document Feedback

13

Product Folder Links: TDP2004