Data Sheet

LT8418

analog.com

Rev 0

7 of 19

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

12-Ball WLCSP Package

Package Size: 1.67mm x 1.67mm, Ball Diameter: 0.26mm, Ball Pitch Size: 0.4mm

Figure 3. Pin Diagram

Pin Descriptions

Table 4. Pin Descriptions

PIN

NAME

DESCRIPTION

A1

BGN

Pull-down branch in bottom side split gate driver output. Adding a resistor from BGN to GaN

FET’s gate can program the turn-off strength of the bottom side GaN FET.

A2

GND

Ground. Connect this pin to the source of the bottom side GaN FET with low inductance and

resistance.

A3, C41

VCC

Power supply for the internal control circuitry and gate drivers. Locally bypassing this pin to

ground with a minimum 4.7µF ceramic capacitor.

A4

INB

PWM input to control bottom-side gate driver. INB is TTL input logic compatible, with a default

200 kΩ pull-down resistance internally. Leave it open or tie it to ground when it is not used.

B1

BGP

Pull-up branch in bottom side split gate driver output. Adding a resistor from BGP to GaN FET’s

gate can program the turn-on strength of the bottom side GaN FET.

B4

INT

PWM input to control top-side gate driver. INT is TTL input logic compatible, with a default 200

kΩ pull-down resistance internally. Leave it open or tie it to ground when it is not used. The

minimum input pulse width for INT is 11ns.

C1, D41

SW

Switch Node. Connect SW to the source of the top synchronous GaN FET and the bottom

terminal of the bootstrap capacitor with low inductance and resistance.

D1

TGN

Pull-down branch in top side split gate driver output. Adding a resistor from TGN to the GaN

FET’s gate can program the turn-off strength of the top side GaN FET.

D2

TGP

Pull-up branch in top side split gate driver output. Adding a resistor from TGP to the GaN FET’s

gate can program the turn-on strength of the top side GaN FET.

D3

BST

Bootstrap Floating Driver Supply. The BST pin has an on-die bootstrap switch from the VCC, and

an external bootstrap capacitor to the SW pin can be used to provide a stable and well-

balanced bootstrap voltage for the top side gate driver. Locally bypass this pin to SW with a

minimum 100nF ceramic capacitor.

1

A3 and C4 are internally connected. C1 and D4 are internally connected.

BGN GND

VCC

INB

1

2

3

4

BGP

INT

SW

VCC

TGN

TGP

BST

SW

A

B

C

D

LT8418

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