8.4 Layout

8.4.1 Layout Guidelines

• Make sure the VIN and GND traces are as wide as possible to reduce trace impedance. The wide areas are

also an advantage from the view point of heat dissipation.

• Place the input capacitor and output capacitor as close to the device as possible to minimize trace

impedance.

• Provide sufficient vias for the input capacitor and output capacitor.

• Connect a separate VOUT path to VOS pin.

• Place a voltage feedback loop away from the high-voltage switching trace, and preferably has ground shield.

• Make sure the GND trace between the output capacitor and the GND pin are as wide as possible to minimize

the trace impedance.

8.4.2 Layout Example

EN

VIN

VOUT

GND

COUT

CIN

VIA (connect to another layer)

VIN

EN

VOS

PG

PGND

VOUT

SW

GND

The line in another layer

Figure 8-12. Layout Guide

TPSM861253

SLUSFD2A – SEPTEMBER 2023 – REVISED JANUARY 2024

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