PCD5041HZ datasheet(15/28 Pages) PHILIPS

15 / 28 page

1996 Oct 31

Philips Semiconductors

Objective speciﬁcation

DECT burst mode controller

PCD5041

The ‘DPLL_sync’ indication should only be used, when

‘SlotSync’ is active. It indicates that the last 4 bits of the

pre-amble field (the training sequence) are received

correctly, and thus indicates that the DPLL was in lock

(synchronized) in time. If the ‘SlotSync’ is active, and the

‘DPLL_sync’ is not, then a sliding interferer might have

been detected.

If ‘SlotSync’ is not detected, effectively no data is received

in that slot. This implies a ‘fast mute’ because speech data

received in the previous frame is not destroyed.

6.5.9

CIPHERING MACHINE

The description of the cipher machine is subject to

confidentiality. The specification of its algorithms are

delivered by ETSI under the terms of a Non-Disclosure

Agreement.

The cipher machine is under control of the TBC, which is

implemented in the PCC. The cipher machine generates

2 fields of ciphering bits:

• A_cipher (40 bits) for A-field messages (ciphers tail

only)

• B_cipher (320 bits) for speech in B-field.

The transmitted ciphered bits are then:

• A_ciphered: = A XOR A_cipher

• B_ciphered: = B XOR B_cipher.

On reception by the peer end point, deciphering consists

of the same operation thanks to the synchronous

generation of A_cipher and B_cipher.

The cipher machine is time-multiplexed on a slot basis.

Initially, the Initialisation Vector (IV) and the key must be

loaded into the cipher machine. Transfer of the IV and key

from the common data area to the cipher machine is done

Fig.11 Cipher machine and its sources.

handbook, halfpage

MBH714

KEY

64 BITS

CIPHER

MACHINE

A_cipher

(40 bits)

B_cipher

(320 bits)

KEY

64 BITS

automatically by the cipher machine. The contents of the

memory space where IV and key are found, are the

responsibility of the PCC, and the external

microprocessor.

6.5.10

COMPARATOR/DATA SLICER ON PCD5041HZ

The PCD5041HZ contains a comparator/data slicer.

The comparator is a stand-alone circuit. No connections

other than power supply are made internally. The

comparator can be used as a data slicer for the receiver

input. The delay requirements listed in Chapter 8 were

derived from this application. Another use of the

comparator is in a successive approximation A/D

converter to indicate battery low-voltage condition, or in a

power-on-reset circuit.

When the signal COMP_NE is LOW the comparator is

enabled. When COMP_NE is HIGH the comparator is

disabled, and the circuit consumes no power. If the

comparator is used as a data slicer for the receiver input,

the R_DATA is connected to COMP_OUT, the COMP_NE

is connected to R_ENABLE, both connection are done

externally. The pin COMP_INP is connected to the RF

mixer. A proper bias voltage (from the slicer time constant

control circuit) is connected to COMP_INM. Another use of

the comparator is in a successive approximation A/D

converter for battery voltage detection.

The pins are protected against ESD damaging, with a

protection diode to the positive and negative supply rail.

The input pin COMP_NE has a pull-up resistor which

keeps the comparator in power-down mode by default.

Fig.12 Circuit schematic of the comparator/data

slicer.

handbook, halfpage

MBH715

COMP_INP

COMP_INM

COMP_OUT

COMP_NE

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