PCE84C486 datasheet(9/36 Pages) PHILIPS

9 / 36 page

1996 Feb 21

Philips Semiconductors

Objective speciﬁcation

Microcontrollers for digital auto-sync and

VST TV controller applications

PCE84C486; PCE84C487

RESET

To initialize the microcontroller to a defined state a reset

operation is performed. A reset can be generated in three

ways:

• applying an external signal to the RESET pin

• via Power-on-reset circuitry

• by the Watchdog Timer.

6.1

External reset using the RESET pin

An active LOW signal from an external logic device will

reset the device. The signal must be maintained long

enough to allow VDD to reach its fxtal-dependent minimum

operating voltage.

6.2

Power-on-reset

A Power-on-reset can be generated using an external RC

circuit. To avoid overload of the internal diode, an external

diode should be added in parallel if CRESET ≥ 2.2 µF.

The RC circuit is shown in Fig.5.

6.3

Watchdog Timer reset

An overflow of the Watchdog Timer will cause the device

to be reset. The operation of the Watchdog Timer is

described in Chapter 12.

Fig.5 External components for RESET pin.

handbook, halfpage

PCA84C8XX

internal reset

MLC259

RESET

( 100 k

Ω)

6.4

Reset trip level

The RESET trip voltage level for both the PCE84C486 and

PCE84C487 is masked to 1.3 V.

6.5

Reset status

• Derivative Registers reset status; see Table 8 for details

• Program Counter 00H

• Memory Bank 0

• Register Bank 0

• Stack Pointer 00H

• All interrupts disabled

• Timer/event counter 1 stopped and cleared

• Timer pre-scaler modulo-32 (PS = 0)

• Timer flag cleared

• Serial I/O interface disabled (ESO = 0) and in slave

receiver mode

• Idle and Stop mode cleared.

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