ST92F124 datasheet(366/429 Pages) STMICROELECTRONICS

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10-BIT ANALOG TO DIGITAL CONVERTER (ADC)

10.11.5 Register Description

DATA REGISTERS (DiHR/DiLR)

The conversion results for the 16 available chan-

nels are loaded into the 32 Data Registers (two for

each channel) following conversion of the corre-

sponding analog input.

CHANNEL 0 DATA HIGH REGISTER (D0HR)

R240 - Read/Write

Reset Value: undefined

Bits 7:0 = D0.[9:2]: Channel 0 9:2 bit Data

CHANNEL 0 DATA LOW REGISTER (D0LR)

R241 - Read/Write

Reset Value: xx00 0000

Bits 7:6 = D0.[1:0]: Channel 0 1:0 bit Data

Bits 5:0 = Reserved, forced by hardware to 0.

CHANNEL 1 DATA HIGH REGISTER (D1HR)

R242 - Read/Write

Reset Value: undefined

Bits 7:0 = D1.[9:2]: Channel 1 9:2 bit Data

CHANNEL 1 DATA LOW REGISTER (D1LR)

R243 - Read/Write

Reset Value: xx00 0000

Bits 7:0 = D1.[1:0]: Channel 1 1:0 bit Data

Bits 5:0 = Reserved, forced by hardware to 0.

CHANNEL 2 DATA HIGH REGISTER (D2HR)

R244 - Read/Write

Reset Value: undefined

Bits 7:0 = D2.[9:2]: Channel 2 9:2 bit Data

CHANNEL 2 DATA LOW REGISTER (D2LR)

R245 - Read/Write

Reset Value: xx00 0000

Bits 7:0 = D2.[1:0]: Channel 2 1:0 bit Data

Bits 5:0 = Reserved, forced by hardware to 0.

CHANNEL 3 DATA HIGH REGISTER (D3HR)

R246 - Read/Write

Reset Value: undefined

Bits 7:0 = D3.[9:2]: Channel 3 9:2 bit Data

CHANNEL 3 DATA LOW REGISTER (D3LR)

R247 - Read/Write

Reset Value: xx00 0000

Bits 7:0 = D3.[1:0]: Channel 3 1:0 bit Data

Bits 5:0 = Reserved, forced by hardware to 0.

D0.9

D0.8

D0.7

D0.6

D0.5

D0.4

D0.3

D0.2

D0.1

D0.0

000

D1.9

D1.8

D1.7

D1.6

D1.5

D1.4

D1.3

D1.2

D1.1

D1.0

000

D2.9

D2.8

D2.7

D2.6

D2.5

D2.4

D2.3

D2.2

D2.1

D2.0

000

D3.9

D3.8

D3.7

D3.6

D3.5

D3.4

D3.3

D3.2

D3.1

D3.0

000

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