PCF8576CUSLASH2 datasheet(20/44 Pages) PHILIPS

20 / 44 page

1998 Jul 30

Philips Semiconductors

Product speciﬁcation

Universal LCD driver for low multiplex

rates

PCF8576C

CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for bidirectional, two-line communication

between different ICs or modules. The two lines are a

serial data line (SDA) and a serial clock line (SCL). Both

lines must be connected to a positive supply via a pull-up

resistor when connected to the output stages of a device.

Data transfer may be initiated only when the bus is not

busy.

7.1

Bit transfer (see Fig.12)

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the

HIGH period of the clock pulse as changes in the data line

at this time will be interpreted as a control signal.

7.2

Start and stop conditions (see Fig.13)

Both data and clock lines remain HIGH when the bus is not

busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock

is HIGH is defined as the STOP condition (P).

7.3

System conﬁguration (see Fig.14)

A device generating a message is a ‘transmitter’, a device

receiving a message is the ‘receiver’. The device that

controls the message is the ‘master’ and the devices which

are controlled by the master are the ‘slaves’.

7.4

Acknowledge (see Fig.15)

The number of data bytes transferred between the START

and STOP conditions from transmitter to receiver is

unlimited. Each byte of eight bits is followed by an

acknowledge bit. The acknowledge bit is a HIGH level

signal put on the bus by the transmitter during which time

the master generates an extra acknowledge related clock

pulse. A slave receiver which is addressed must generate

an acknowledge after the reception of each byte. Also a

master receiver must generate an acknowledge after the

reception of each byte that has been clocked out of the

slave transmitter. The device that acknowledges must

pull-down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse (set-up and

hold times must be taken into consideration). A master

receiver must signal an end of data to the transmitter by

not generating an acknowledge on the last byte that has

been clocked out of the slave. In this event the transmitter

must leave the data line HIGH to enable the master to

generate a STOP condition.

7.5

PCF8576C I2C-bus controller

The PCF8576C acts as an I2C-bus slave receiver. It does

not initiate I2C-bus transfers or transmit data to an I2C-bus

master receiver. The only data output from the PCF8576C

are the acknowledge signals of the selected devices.

Device selection depends on the I2C-bus slave address,

on the transferred command data and on the hardware

subaddress.

In single device application, the hardware subaddress

inputs A0, A1 and A2 are normally tied to VSS which

defines the hardware subaddress 0. In multiple device

applications A0, A1 and A2 are tied to VSS or VDD in

accordance with a binary coding scheme such that no two

devices with a common I2C-bus slave address have the

same hardware subaddress.

In the power-saving mode it is possible that the PCF8576C

is not able to keep up with the highest transmission rates

when large amounts of display data are transmitted. If this

situation occurs, the PCF8576C forces the SCL line LOW

until its internal operations are completed. This is known

as the ‘clock synchronization feature’ of the I2C-bus and

serves to slow down fast transmitters. Data loss does not

occur.

7.6

Input ﬁlters

To enhance noise immunity in electrically adverse

environments, RC low-pass filters are provided on the

SDA and SCL lines.

7.7

I2C-bus protocol

Two I2C-bus slave addresses (0111000 and 0111001) are

reserved for the PCF8576C. The least significant bit of the

slave address that a PCF8576C will respond to is defined

by the level tied at its input SA0 (pin 10). Therefore, two

types of PCF8576C can be distinguished on the same

I2C-bus which allows:

1. Up to 16 PCF8576Cs on the same I2C-bus for very

large LCD applications.

2. The use of two types of LCD multiplex on the same

I2C-bus.

The I2C-bus protocol is shown in Fig.16. The sequence is

initiated with a START condition (S) from the I2C-bus

master which is followed by one of the two PCF8675C

slave addresses available. All PCF8576Cs with the

corresponding SA0 level acknowledge in parallel with the

slave address but all PCF8576Cs with the alternative SA0

level ignore the whole I2C-bus transfer.

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