PCF8576CUSLASH2 datasheet(25/44 Pages) PHILIPS

25 / 44 page

1998 Jul 30

Philips Semiconductors

Product speciﬁcation

Universal LCD driver for low multiplex

rates

PCF8576C

Table 10 Load data pointer option 1

Table 11 Device select option 1

Table 12 Bank select option 1

Table 13 Bank select option 2

DESCRIPTION

BITS

6 bit binary value of 0 to 39

P5 P4 P3 P2 P1 P0

DESCRIPTION

BITS

3 bit binary value of 0 to 7

STATIC

1 : 2 MUX

BIT I

RAM bit 0

RAM bits 0 and 1

RAM bit 2

RAM bits 2 and 3

STATIC

1 : 2 MUX

BIT O

RAM bit 0

RAM bits 0 and 1

RAM bit 2

RAM bits 2 and 3

Table 14 Blink option 1

Table 15 Blink option 2

BLINK FREQUENCY

BITS

BF1

BF0

Off

2Hz

1Hz

0.5 Hz

BLINK MODE

BIT A

Normal blinking

Alternation blinking

7.9

Display controller

The display controller executes the commands identified

by the command decoder. It contains the status registers

of the PCF8576C and co-ordinates their effects.

The controller is also responsible for loading display data

into the display RAM as required by the filling order.

7.10

Cascaded operation

In large display configurations, up to 16 PCF8576Cs can

be distinguished on the same I2C-bus by using the 3-bit

hardware subaddress (A0, A1 and A2) and the

programmable I2C-bus slave address (SA0). When

cascaded PCF8576Cs are synchronized so that they can

share the backplane signals from one of the devices in the

cascade. Such an arrangement is cost-effective in large

LCD applications since the backplane outputs of only one

device need to be through-plated to the backplane

electrodes of the display. The other PCF8576Cs of the

cascade contribute additional segment outputs but their

backplane outputs are left open-circuit (Fig.18).

The SYNC line is provided to maintain the correct

synchronization between all cascaded PCF8576Cs. This

synchronization is guaranteed after the power-on reset.

The only time that SYNC is likely to be needed is if

synchronization is accidentally lost (e.g. by noise in

adverse electrical environments; or by the definition of a

multiplex mode when PCF8576Cs with differing SA0

levels are cascaded). SYNC is organized as an

input/output pin; the output selection being realized as an

open-drain driver with an internal pull-up resistor.

A PCF8576C asserts the SYNC line at the onset of its last

active backplane signal and monitors the SYNC line at all

other times. Should synchronization in the cascade be

lost, it will be restored by the first PCF8675C to assert

SYNC. The timing relationship between the backplane

waveforms and the SYNC signal for the various drive

modes of the PCF8576C are shown in Fig.19.

For single plane wiring of packaged PCF8576Cs and

chip-on-glass cascading, see Chapter “Application

information”.

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