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PCK2021 Datasheet(PDF) 8 Page - NXP Semiconductors |
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PCK2021 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 15 page  Philips Semiconductors Product data PCK2021 CK00 (100/133 MHz) spread spectrum differential system clock generator 2001 Oct 11 8 AC ELECTRICAL CHARACTERISTICS VDD3 = 3.3 V ±5%; fcrystal = 14.31818 MHz Host clock outputs Tamb = 0 to +70 °C; see Figure 1 for waveforms and Figure 6 for test setup. LIMITS SYMBOL PARAMETER 133 MHz MODE 100 MHz MODE UNITS NOTES MIN MAX MIN MAX tPERIOD HOST CLK average period 7.5 7.65 10.0 10.2 ns 11, 14, 19 Abs Min Period Absolute minimum host clock period 7.35 N/A 9.85 N/A ns 11, 14, 19 tRISE HOST CLK rise time 175 700 175 700 ns 11, 15, 19 tFALL HOST CLK fall time 175 700 175 700 ps 11, 15, 19 tJITTER HOST_CLK cycle-to-cycle jitter — 150 — 150 ps 11, 12, 14, 19 DUTY CYCLE Output duty cycle 45 55 45 55 % 11, 14, 19 tSKEW HOST CLK pin-to-pin skew — 150 — 110 ps 11, 14, 19 Vcrossover 45% VOH 55% VOH 45% VOH 55% VOH V 11, 14, 19 REFER TO NOTES ON PAGE 10. USB clock output, 48MHz Tamb = 0 to +70 °C; lump capacitance test load = 20 pF LIMITS SYMBOL PARAMETER 48 MHz MODE UNITS NOTES MIN MAX f Frequency, actual 48.000 MHz 4 fD Deviation from 48 MHz –0 +167 ppm 4 tRISE 3V48MHZCLK rise time 1.0 4.0 ns 8, 19 tFALL 3V48MHZCLK fall time 1.0 4.0 ns 8, 19 tJITTER Cycle-to-cycle jitter — 450 ps 17, 19 DUTY CYCLE Output duty cycle 45 55 % 17, 19 REFER TO NOTES ON PAGE 10. PCI Outputs Tamb = 0 to +70 °C SYMBOL PARAMETER LIMITS UNITS NOTES SYMBOL PARAMETER MIN MAX UNITS NOTES tPERIOD Period 30.0 N/A ns 2, 3, 9, 19 tHIGH High time 12.0 N/A ns 5, 10, 19 tLOW Low time 12.0 N/A ns 6, 10, 19 tRISE Rise time 0.5 2.0 ns 8, 19 tFALL Fall time 0.5 2.0 ns 17, 19 DUTY CYCLE Duty cycle 45 55 % 17, 19 tJITTER Cycle-to-cycle jitter — 200 ps 17, 19 tSKEW Pin-to-pin skew — 150 ps 2 REFER TO NOTES ON PAGE 10. |
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