DSP56362P datasheet(94/152 Pages) FREESCALE

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Timer Timing

DSP56362 Technical Data, Rev. 4

3-68

Freescale Semiconductor

3.16

Timer Timing

Figure 3-45 TIO Timer Event Input Restrictions

Figure 3-46 Timer Interrupt Generation

Table 3-26 Timer Timing1

1 V

CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF

No.

Characteristics

Expression

100 MHz

Unit

Min

Max

480

TIO Low

× T

C + 2.0

22.0

—

481

TIO High

× T

C + 2.0

22.0

—

482

Timer setup time from TIO (Input) assertion to CLKOUT rising edge

9.0

10.0

483

Synchronous timer delay time from CLKOUT rising edge to the

external memory access address out valid caused by first interrupt

instruction execution

10.25

× T

C + 1.0

103.5

—

484

CLKOUT rising edge to TIO (Output) assertion

• Minimum

•Maximum

0.5

× T

C + 3.5

0.5

× T

C + 19.8

8.5

—

24.8

485

CLKOUT rising edge to TIO (Output) deassertion

• Minimum

•Maximum

0.5

× T

C + 3.5

0.5

× T

C + 19.0

8.5

—

24.8

TIO

481

480

AA0492

CLKOUT

TIO (Input)

First Interrupt Instruction Execution

Address

482

483

AA0493

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