M68HC11K datasheet(39/290 Pages) FREESCALE

39 / 290 page

Pin Description

Mode Selection, Instruction Cycle Reference, and Standby Power (MODA/LIR and MODB/VSTBY)

M68HC11K Family

Technical Data

MOTOROLA

Pin Description

required for wire-OR configuration. Software can change the triggering

to edge sensitive.

XIRQ interrupts can be non-maskable after reset initialization. Out of

reset, the X bit in the CCR is set, masking XIRQ interrupts. Once

software clears the X bit, it cannot be reset, and the XIRQ interrupts

become non-maskable. The XIRQ input is level sensitive only. XIRQ is

often used as a power-loss detect interrupt.

Whenever IRQ or XIRQ is used with multiple interrupt sources, each

source must drive the interrupt input with an open-drain type of driver to

avoid contention between outputs. There should be a single pullup

resistor near the MCU interrupt pin (typically 4.7 k

Ω). There must also be

an interlock mechanism at each interrupt source which holds the

interrupt line low until the MCU recognizes and acknowledges the

interrupt request. If any interrupt sources are still pending after the MCU

services a request, the interrupt line will remain low, interrupting the

MCU again as soon as the I bit in the MCU is cleared (normally upon

return from an interrupt). Interrupt mechanisms are explained further in

Section 5. Resets and Interrupts.

On EPROM devices, the XIRQ pin also functions as the high-voltage

supply, VPP, during EPROM or OTPROM programming.

CAUTION:

Ensure that the voltage level at this pin is equal to VDD during normal

operation to avoid programming accidents.

2.9 Mode Selection, Instruction Cycle Reference, and Standby Power

(MODA/LIR and MODB/VSTBY)

During reset, MODA and MODB select one of four operating modes:

1. Single-chip

2. Expanded

3. Bootstrap

4. Special test

For full descriptions of these modes, refer to 4.5 Operating Modes.

Freescale Semiconductor, Inc.

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M68HC11K Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc