PAC7112 datasheet(24/56 Pages) FREESCALE

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MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2

Preliminary

Electrical Characteristics

Freescale Semiconductor

3.10 Analog-to-Digital Converter

Table 26 and Table 27 show conditions under which the ATD operates. The following constraints exist to

obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists because the

sample buffer amplifier cannot drive beyond the ATD power supply levels. If the input level goes outside of

this range it will effectively be clipped.

Table 26. ATD Operating Characteristics in 5.0 V Range

Conditions shown in Table 7 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

D Reference Potential

Low

High

VRL

VRH

VSSA

VDDA ÷ 2

—

VDDA ÷ 2

VDDA

C Differential Reference Voltage 1

NOTES:

1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V

VRH – VRL

4.50

5.00

5.50

D ATD Clock Frequency

fATDCLK

0.5

—

2.0

MHz

D ATD 10-bit Conversion PeriodfATDCLK Cycles

@ 2.0MHz fATDCLK

2. Minimum time assumes a sample period of 2 ATD clocks; maximum time assumes a sample period of 16 ATD clocks.

NCONV10

TCONV10

—

Cycles

μs

D ATD 8-bit Conversion PeriodfATDCLK Cycles

@ 2.0MHz fATDCLK

NCONV8

TCONV8

—

Cycles

μs

D Stop Recovery Time (VDDA = 5.0 V)

TREC

——

μs

P Reference Supply current 1 ATD module on

IREF

—

0.200

0.255

P Reference Supply current 2 ATD modules on

IREF

—

0.400

0.510

Table 27. ATD Operating Characteristics in 3.3 V Range

Conditions shown in Table 7, with VDDX = 3.3 V –5/+10% and a temperature maximum of +140°C unless otherwise

noted.

Num C

Rating

Symbol

Min

Typ

Max

Unit

D Reference Potential

Low

High

VRL

VRH

VSSA

VDDA ÷ 2

—

VDDA ÷ 2

VDDA

C Differential Reference Voltage 1

NOTES:

1. Full accuracy is not guaranteed when differential voltage is less than 3.15 V

VRH – VRL

3.15

3.3

3.6

D ATD Clock Frequency

fATDCLK

0.5

—

2.0

MHz

D ATD 10-bit Conversion PeriodfATDCLK Cycles

@ 2.0MHz fATDCLK

2. Minimum time assumes a sample period of 2 ATD clocks; maximum time assumes a sample period of 16 ATD clocks.

NCONV10

TCONV10

—

Cycles

μs

D ATD 8-bit Conversion PeriodfATDCLK Cycles

@ 2.0MHz fATDCLK

NCONV8

TCONV8

—

Cycles

μs

D Stop Recovery Time (VDDA = 3.3 V)

TREC

——

μs

P Reference Supply current 1 ATD module on

IREF

—

0.130

0.170

P Reference Supply current 2 ATD modules on

IREF

—

0.260

0.340

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