PAC7112 datasheet(52/56 Pages) FREESCALE

52 / 56 page

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2

Preliminary

Mechanical Information

Freescale Semiconductor

v1.0

14-Sep-04

(continued)

Section 3, “Electrical Characteristics”

• Section 3.2, “Absolute Maximum Ratings”

— A1a renamed to VDDX

— A4 “rating” changed to Analog (from ATD)

— A9 minimum changed to –0.3

— A12 maximum value removed, footnote reference added

— Table 8, Table 9 footnotes added regarding VDD5/VSS5

• Section 3.4, “Operating Conditions”

— C1 renamed to VDDX

— C4 added (C5 to C11b renumbered)

— C8 maximum changed from 40 MHz to 50 MHz

• Section 3.5, “Input/Output Characteristics”

— Table 8 spec D4 updated (from TBD)

— Table 9 spec E4 changed to 1

μA to match D4

• Section 3.6, “Power Dissipation and Thermal Characteristics”

— Reworked Equation 1 through Equation 4 and supporting text

— Section 3.6.1 and Table 10 name changed from “Power Dissipation...”

• Section 3.7, “Power Supply”

— Added MAC71x1 designation and footnotes to Table 15 / Table 16

— Table 15 designated for 40 MHz, and

– Numerous TBD entries replaced with values

– Run Supply Current collapsed from fifteen spec items to one

– Removed separate Core/Regulator/Pins specs for Run/Pseudo Stop/Stop modes

– F1 and F3 descriptions changed

– F1, F2, F3 and F4 values updated

— Table 16 added for 50 MHz specifications

— Table 17, deleted IREG spec (Regulator Current in Reduced Power, Shutdown Modes)

— Table 18, VDD2.5 load capacitance typical changed, with clarification footnote

• Section 3.8, “Clock and Reset Generator”

— Table 19 updates

– Changed specs J1b and J6 maximum from 40 MHz to 50 MHz

– Reversed polarity of XCLKS reference in footnote (3)

– J1b maximum changed to 40 MHz

–VDCBIAS removed

– Added footnote to define tfsys as 1 ÷ fSYS for use elsewhere in the document

— Updated Section 3.8.2, “PLL Filter Characteristics”

— Table 20 updates

– Changed spec K3 maximum from 40 MHz to 50 MHz

– Added footnote to define tfsys as 1 ÷ fSYS for use elsewhere in the document

— Table 23 updates

–Removed VPORR and VPORA, as they duplicated H6

–Removed tWRS

• Section 3.9, “External Bus Timing”

— Table 24 updates

– M1 minimum changed from 25 ns to 20 ns (Figure 6 also updated)

– Reworded footnote (1)

– Added footnote (2) to define tCYC as 1 ÷ CLKOUT

— Table 25 updates

– Added footnote (1)

– Consolidated previous NOTES into footnote (2), (Figure 7, Figure 8 also updated)

7, 8

Revision History (continued)

Version No.

Release Date

Description of Changes

Page

Numbers

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