LR4102 datasheet(20/32 Pages) LSI

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TinyRISC LR4102 Microprocessor

Table 8

AC Input Timing with respect to rising edge of PBCLKP1

1. With 65 pF load

2. This signal is related to the system clock, but not to the FAPI bus (see

Figure 5 note).

3. This signal is related to both the system clock and the FAPI bus (see

Figure 5 note).

Input Signal

Setup

Hold

Units

CBEN[3:0]

7.2

1.4

DEVSELN

4.7

2.2

FADP[31:0]3

2.9

2.7

FRAMEN

7.4

2.2

GP[5:0]2

2.8

2.6

GPIO[3:0]2

1.8

2.8

IRDYN

7.5

1.9

REQN

3.5

1.5

STOPN

4.7

1.7

TRDYN

4.6

2.0

Table 9

AC Input Timing with respect to rising edge of SDCLKP1

1. With 65 pF load.

Input Signal

Setup

Hold

Units

FADP[31:0]

2.0

3.4

Table 10

AC Input Timing with respect to rising edge of TCK

Input

Setup

Hold

Units

TDI_DINT

1.9

1.1

TMS

1.6

0.7

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