Preliminary Technical Data

AD5441

Rev. PrA | Page 5 of 16

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

VREF

2

RFB

3

IOUT

4

GND

8VDD

7CLK

5SRI

5LD

AD5441

TOP VIEW

(Not to Scale)

Figure 3. 8-LeadLFCSP Pin Configuration

AD5441

TOP VIEW

(Not to Scale)

VDD

CLK

SRI

LD

8

7

6

5

Figure 4. 8-Lead MSOP Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Descriptions

1

DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.

2

Internal Matching Feedback Resistor. Connect to external op amp output.

3

4

GND

Analog and Digital Ground.

5

LD

Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register while active low.

See Table 4 for operation.

6

SRI

12-Bit Serial Register Input, data loads directly into the shift register MSB first. Extra leading bits are ignored.

7

CLK

Clock Input, positive-edge clocks data into shift register.

8

Positive Power Supply Input. Specified range of operation 5 V ± 10%.