AD9865BCPRL datasheet(25/48 Pages) AD

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AD9865

Rev. A | Page 25 of 48

RXCLK

RXSYNC

Rx[5:0]

Rx0LSB

Rx1MSB

Rx1LSB

Rx2MSB

Rx3LSB

Rx3MSB

tDv

tDH

Figure 54. Full-Duplex Rx Port Timing

To add flexibility to the full-duplex digital interface port, several

programming options are available in the SPI registers. These

options are listed in Table 14. The timing for the Tx[5:0] and/or

Rx[5:0] ports can be independently changed by selecting either

the rising or falling clock edge as the sampling/validating edge

of the clock. Inverting RXCLK (via Bit 1 or Register 0x05)

affects both the Rx and Tx interface, because they both use

RXCLK.

Table 14. SPI Registers for Full-Duplex Interface

Address (Hex)

Bit

Description

0x05

(2)

OSCIN to RXCLK

(1)

Invert RXCLK

(0)

Disable RXCLK

0x0B

(2)

Rx gain on Tx port

0x0C

(4)

Invert TXSYNC

(3)

Tx 5/5 nibble

(2)

LS nibble first

(1)

TXCLK negative edge

(0)

Twos complement

0x0D

(5)

Rx port three-state

(4)

Invert RXSYNC

(3)

Rx 5/5 nibble

(2)

LS nibble first

(1)

RXCLK negative edge

(0)

Twos complement

0x0E

(7)

Low drive strength

The default Tx and Rx data input formats are twos complement,

but can be changed to straight binary. The default TXSYNC and

RXSYNC settings can be changed such that the first nibble of

the word appears while TXSYNC, RXSYNC, or both are high.

Also, the least significant nibble can be selected as the first

nibble of the word (LS nibble first). The output driver strength

can also be reduced for lower data rate applications.

For the AD9865, the most significant nibble defaults to 6 bits,

and the least significant nibble defaults to 4 bits. This can be

changed so that the least significant nibble and most significant

nibble have 5 bits each. To accomplish this, set the 5/5 nibble bit

in Register 0x0C and Register 0x0D and use data pins Tx[5:1]

and Rx[5:1].

Figure 55 shows a possible digital interface between an ASIC

and the AD9865. The AD9865 serves as the master generating

the required clocks for the ASIC. This interface requires that the

ASIC reserve 16 pins for the interface, assuming a 6-bit nibble

width and the use of the Tx port for RxPGA gain control. Note

that the ASIC pin allocation can be reduced by 3, if a 5-bit

nibble width is used and the gain (or gain strobe) of the RxPGA

is controlled via the SPI port.

Tx DIGITAL

FILTER

10/12

AD9865/AD9866

FROM

RxADC

10/12

RXSYNC

TXSYNC

TX_SYNC

RXCLK

CLKOUT1

CLKOUT2

CLKIN

DIGITAL ASIC

OSCIN

FROM

CRYSTAL

OR MASTER CLK

GAIN

OPTIONAL

Tx Data[5:0]

Rx Data[5:0]

Rx[5:0]

RX_SYNC

Tx[5:0]

RxPGA

Figure 55. Example of a Full-Duplex Digital Interface

with Optional RxPGA Gain Control via Tx[5:0]

RxPGA CONTROL

The AD9865 contains a digital PGA in the Rx path that is used

to extend the dynamic range. The RxPGA can be programmed

over −12 dB to +48 dB with 1 dB resolution using a 6-bit word,

and with a 0 dB setting corresponding to a 2 V p-p input signal.

The 6-bit word is fed into a LUT that is used to distribute the

desired gain over three amplification stages within the Rx path.

Upon power-up, the RxPGA gain register is set to its minimum

gain of −12 dB. The RxPGA gain mapping is shown in Figure 56.

Table 15 lists the SPI registers pertaining to the RxPGA.

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