AD9865BCPRL datasheet(29/48 Pages) AD

29 / 48 page

AD9865

Rev. A | Page 29 of 48

Applications demanding the highest spectral performance

and/or lowest power consumption can use the TxDAC output

directly. The TxDAC is capable of delivering a peak signal

power-up to 10 dBm while maintaining respectable linearity

performance, as shown in Figure 27 through Figure 38. For

power-sensitive applications requiring the highest Tx power

efficiency, the TxDAC’s full-scale current output can be reduced

to as low as 2 mA, and its load resistors sized to provide a

suitable voltage swing that can be amplified by a low-power op-

amp-based driver.

Most applications requiring higher peak signal powers (up to

23 dBm) should consider using the IAMP. The IAMP can be

configured as a current source for loads having a well defined

impedance (50 Ω or 75 Ω systems), or a voltage source (with the

addition of a pair of npn transistors) for poorly defined loads

having varying impedance (such as power lines).

Figure 62 shows the equivalent schematic of the TxDAC and

IAMP. The TxDAC provides a differential current output

appearing at IOUTP+ and IOUTP−. It can be modeled as a

differential current source generating a signal-dependent ac

current, when ∆IS has a peak current of I along with two dc

current sources, sourcing a standing current equal to I. The full-

scale output current, IOUTFS, is equal to the sum of these

standing current sources (IOUTFS = 2 × I).

±∆I

TxDAC

REFADJ

REFIO

IOUTP+

IOUTP–

I +

∆I

I–

∆I

IOFF1

RSET 0.1µF

IOFF1

IOFF2

IAMP

Figure 62. Equivalent Schematic of TxDAC and IAMP

The value of I is determined by the RSET value at the REFADJ

pin along with the Tx path’s digital attenuation setting. With

0 dB attenuation, the value of I is

I = 16 × (1.23/RSET)

(1)

For example, an RSET value of 1.96 kΩ results in I equal to

10.0 mA with IOUTFS equal to 20.0 mA. Note that the REFIO

pin provides a nominal band gap reference voltage of 1.23 V

and should be decoupled to analog ground via a 0.1 µF

capacitor.

The differential current output of the TxDAC is always con-

nected to the IOUTP pins, but can be directed to the IAMP by

clearing Bit 0 of Register 0x0E. As a result, the IOUTP pins

must remain completely open, if the IAMP is to be used. The

IAMP contains two sets of current mirrors that are used to

replicate the TxDAC’s current output with a selectable gain. The

first set of current mirrors is designated as the primary path,

providing a gain factor of N that is programmable from 0 to 4 in

steps of 1 via Bits 2:0 of Register 0x10 with a default setting of

N = 4. Bit 7 of this register must be set to overwrite the default

settings of this register. This differential path exhibits the best

linearity performance (see Figure 42) and is available at the

IOUTN+ and IOUTN− pins. The maximum peak current per

output is 100 mA and occurs when the TxDAC’s standing

current, I, is set for 12.5 mA (IOUTFS = 25 mA).

The second set of current mirrors is designated as the secon-

dary path providing a gain factor of G that is programmable

from 0 to 36 via Bits 6:4 of Register 0x10 and Bits 6:0 of Register

0x11 with a default setting of G = 12. This differential path is

intended to be used in the voltage mode configuration to bias

the external npn transistors, because it exhibits degraded

linearity performance (see Figure 43) relative to the primary

path. It is capable of sinking up to 180 mA of peak current into

either its IOUTG+ or IOUTG− pins. The secondary path

actually consists of three gain stages (G1, G2, and G3), which

are individually programmable as shown in Table 19. While

many permutations may exist to provide a fixed gain of G, the

linearity performance of a secondary path remains relatively

independent of the various individual gain settings that are

possible to achieve a particular overall gain factor.

Both sets of mirrors sink current, because they originate from

NMOS devices. Therefore, each output pin requires a dc current

path to a positive supply. Although the voltage output of each

output pin can swing between 0.5 V and 7 V, optimum ac per-

formance is typically achieved by limiting the ac voltage swing

with a dc bias voltage set between 4 to 5 V. Lastly, both the

standing current, I, and the ac current, ∆IS, from the TxDAC are

amplified by the gain factor (N and G) with the total standing

current drawn from the positive supply being equal to

2 × (N = G) × I

Programmable current sources IOFF1 and IOFF2 via Register 0x12

can be used to improve the primary and secondary path

mirrors’ linearity performance under certain conditions by

increasing their signal-to-standing current ratio. This feature

provides a marginal improvement in distortion performance

under large signal conditions when the peak ac current of the

reconstructed waveform frequently approaches the dc standing

current within the TxDAC (0 to −1 dBFS sine wave) causing the

internal mirrors to turn off. However, the improvement in

distortion performance diminishes as the crest factor (peak-to-

rms ratio) of the ac signal increases. Most applications can

disable these current sources (set to 0 mA via Register 0x12) to

reduce the IAMP’s current consumption.

AD9865BCPRL Datasheet(PDF) 29 Page - Analog Devices

AD9865BCPRL Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL