NE571 datasheet(6/11 Pages) PHILIPS

6 / 11 page

Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

NOTES:

GAIN

2R3 VINavg

IB = 140µA

External components

VIN

CIN

VOUT

∆G

CRECT*

RDC

CDC

VREF

SR00682

Figure 8. Basic Compressor

10k

VIN

V+

I = VIN / R1

SR00684

Figure 9. Rectifier Concept

CIRCUIT DETAILS—RECTIFIER

Figure 9 shows the concept behind the full-wave averaging rectifier.

The input current to the summing node of the op amp, VINR1, is

supplied by the output of the op amp. If we can mirror the op amp

output current into a unipolar current, we will have an ideal rectifier.

The output current is averaged by R5, CR, which set the averaging

time constant, and then mirrored with a gain of 2 to become IG, the

gain control current.

Figure 10 shows the rectifier circuit in more detail. The op amp is a

one-stage op amp, biased so that only one output device is on at a

time. The non-inverting input, (the base of Q1), which is shown

grounded, is actually tied to the internal 1.8V VREF. The inverting

input is tied to the op amp output, (the emitters of Q5 and Q6), and

the input summing resistor R1. The single diode between the bases

of Q5 and Q6 assures that only one device is on at a time. To detect

the output current of the op amp, we simply use the collector

currents of the output devices Q5 and Q6. Q6 will conduct when the

input swings positive and Q5 conducts when the input swings

negative. The collector currents will be in error by the

a of Q5 or Q6

on negative or positive signal swings, respectively. ICs such as this

have typical NPN

βs of 200 and PNP βs of 40. The a’s of 0.995 and

0.975 will produce errors of 0.5% on negative swings and 2.5% on

positive swings. The 1.5% average of these errors yields a mere

0.13dB gain error.

At very low input signal levels the bias current of Q2, (typically

50nA), will become significant as it must be supplied by Q5. Another

low level error can be caused by DC coupling into the rectifier. If an

offset voltage exists between the VIN input pin and the base of Q2,

an error current of VOS/R1 will be generated. A mere 1mV of offset

will cause an input current of 100nA which will produce twice the

error of the input bias current. For highest accuracy, the rectifier

should be coupled into capacitively. At high input levels the

β of the

PNP Q6 will begin to suffer, and there will be an increasing error until

the circuit saturates. Saturation can be avoided by limiting the

current into the rectifier input to 250

µA. If necessary, an external

resistor may be placed in series with R1 to limit the current to this

value. Figure 11 shows the rectifier accuracy vs input level at a

frequency of 1kHz.

V+

10k

Q1 Q2

VIN

V–

G +

VIN avg

NOTE:

SR00683

Figure 10. Simplified Rectifier Schematic

At very high frequencies, the response of the rectifier will fall off. The

roll-off will be more pronounced at lower input levels due to the

increasing amount of gain required to switch between Q5 or Q6

conducting. The rectifier frequency response for input levels of

0dBm, -20dBm, and -40dBm is shown in Figure 12. The response at

all three levels is flat to well above the audio range.

–1

–40

–20

RECTIFIER INPUT dBm

SR00685

Figure 11. Rectifier Accuracy

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