Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

7

0

3

10k

1MEG

INPUT = 0dBm

–20dBm

–40dBm

FREQUENCY (Hz)

SR00686

Figure 12. Rectifier Frequency Response vs Input Level

VARIABLE GAIN CELL

Figure 13 is a diagram of the variable gain cell. This is a linearized

output current.

will be linear for small signals, but very non-linear for large signals,

since it is compensating for the non-linearity of the differential pair,

Q1

Q2

Q3

Q4

I

OUT +

I

G

I

1

I

IN +

I

G

V

IN

I

2

R

2

NOTE:

I2 (= 2I1)

280

µA

IG

IIN

VIN

R2

20k

I1

140

µA

V+

V–

SR00687

Figure 13. Simplified

∆G Cell Schematic

The key to the circuit is that this same predistorted drive signal is

pairs of transistors have the same signal applied, their collector

current ratios will be identical regardless of the magnitude of the

currents. This gives us:

I

C1

I

C2

+

I

C4

I

C3

+

I

I

multiplier transfer function,

I

I

G

I

1

I

V

IN

R

2

I

G

I

1

This equation is linear and temperature-insensitive, but it assumes

ideal transistors.

4

3

2

1

.34

–6

0

+6

4mV

3mV

2mV

1mV

INPUT LEVEL (dBm)

VOS = 5mV

SR00688

Figure 14.

∆G Cell Distortion vs Offset Voltage

If the transistors are not perfectly matched, a parabolic, non-linearity

is generated, which results in second harmonic distortion. Figure 14

gives an indication of the magnitude of the distortion caused by a

given input level and offset voltage. The distortion is linearly

proportional to the magnitude of the offset and the input level.

Saturation of the gain cell occurs at a +8dBm level. At a nominal

operating level of 0dBm, a 1mV offset will yield 0.34% of second

harmonic distortion. Most circuits are somewhat better than this,

which means our overall offsets are typically about mV. The

distortion is not affected by the magnitude of the gain control

current, and it does not increase as the gain is changed. This

second harmonic distortion could be eliminated by making perfect

transistors, but since that would be difficult, we have had to resort to

other methods. A trim pin has been provided to allow trimming of the

internal offsets to zero, which effectively eliminated

second harmonic distortion. Figure 15 shows the simple trim

network required.

Figure 16 shows the noise performance of the

∆G cell. The

maximum output level before clipping occurs in the gain cell is

plotted along with the output noise in a 20kHz bandwidth. Note that

the noise drops as the gain is reduced for the first 20dB of gain

reduction. At high gains, the signal to noise ratio is 90dB, and the

total dynamic range from maximum signal to minimum noise is

110dB.

3.6V

VCC

R

20k

6.2k

To THD Trim

≈200pF

SR00689

Figure 15. THD Trim Network