6.5 Thermal Information

THERMAL METRIC(1)

TPSM8281x

UNIT

VCA (JEDEC 51-5)

13 PINS

RθJA

Junction-to-ambient thermal resistance

73.0

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

34.1

°C/W

RθJB

Junction-to-board thermal resistance

20.9

°C/W

ψJT

Junction-to-top characterization parameter

(-1.4)(2)

°C/W

ψJB

Junction-to-board characterization parameter

20.6

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report and Section 12.3 - Thermal Consideration.

(2)

Case top temperature can be higher than temperature of active circuit because of inductor power dissipation. This results in a

negative Junction-to-top characterization parameter.

6.6 Electrical Characteristics

Over operating junction temperature (TJ = -40 °C to +125 °C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and TJ = 25

°C. (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

IQ

Operating Quiescent Current

EN = high, IOUT= 0 mA, Device not

switching

15

21

µA

ISD

Shutdown Current

EN = 0 V

0.11

18

µA

VUVLO

Undervoltage Lockout Threshold

Rising Input Voltage

2.5

2.6

2.75

V

Falling Input Voltage

2.25

2.5

2.6

V

TSD

Thermal Shutdown Temperature

Rising Junction Temperature

170

°C

Thermal Shutdown Hysteresis

15

CONTROL (EN, SS/TR, PG, MODE/SYNC)

VIH

High Level Input Voltage for MODE/

SYNC Pin

1.1

V

VIL

Low Level Input Voltage for MODE/

SYNC Pin

0.3

V

fSYNC

Frequency Range on MODE/SYNC

Pin for Synchronization

1.8

4

MHz

Duty Cycle of Synchronization Signal

at MODE/SYNC Pin

40%

50%

60%

VIH

Input Threshold Voltage for EN pin

Rising EN

1.06

1.1

1.15

V

VIL

Input Threshold Voltage for EN pin

Falling EN

0.96

1.0

1.05

V

ILKG

Input Leakage Current for EN, MODE/

SYNC Pins

EN, MODE/SYNC = VIN or GND

150

nA

VTH_PG

UVP Power Good Threshold

Rising (%VFB)

92%

95%

98%

UVP Power Good Threshold

Falling (%VFB)

87%

90%

93%

OVP Power Good Threshold

Rising (%VFB)

107%

110%

113%

OVP Power Good Threshold

Falling (%VFB)

104%

107%

111%

Power Good De-glitch Time

for a high level to low level transition

on power good

40

µs

VOL_PG

Power Good Output Low Voltage

IPG = 2 mA

0.07

0.3

V

ILKG_PG

Input Leakage Current for PG Pin

VPG = 5 V

100

nA

ISS/TR

SS/TR Pin Source Current

2.1

2.5

2.8

µA

Tracking Gain

VFB / VSS/TR

1

Tracking Offset

FB pin with VSS/TR = 0 V

17

mV

POWER SWITCH

RDS(ON)

High-Side MOSFET ON-Resistance

VIN ≥ 5 V

37

60

mΩ

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