8.3.6 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the

MOSFETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the input

voltage goes below the falling threshold.

8.3.7 Power-Good Output (PG)

The device has a power good output with window comparator. The PG pin goes high impedance after the FB

pin voltage is above 95% and less than 107% of the nominal voltage, and is driven low after the voltage falls

below typically 90% or higher than 110% of the nominal voltage. Table 8-2 shows the typical PG pin logic. The

PG pin is an open-drain output and is specified to sink up to 2mA. The power good output requires a pullup

resistor connected to any voltage rail less than VIN. The PG signal can be used for sequencing of multiple rails

by connecting to the EN pin of other converters. If not used, the PG pin can be left floating or connected to GND.

Table 8-2. Power Good Pin Logic

DEVICE STATE

PG LOGIC STATUS

HIGH IMPEDANCE

LOW

Enabled (EN = High)

0.57V ≤ VFB ≤ 0.642V

√

VFB < 0.54V or VFB > 0.66V

√

Shutdown (EN = Low)

√

UVLO

2V ≤ VIN < VUVLO

√

Thermal Shutdown

TJ > TJSD

√

Power Supply Removal

VIN < 2V

√

The PG pin has a 40μs deglitch time on the falling edge.

8.3.8 Thermal Shutdown

The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 170°C

(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and

PG goes low. When TJ decreases below the hysteresis amount of typically 15°C, the converter resumes normal

operation, beginning with soft start. During PFM, the thermal shutdown is not active.

8.4 Device Functional Modes

8.4.1 Pulse Width Modulation (PWM) Operation

The TPSM8281x has two operating modes: Forced PWM mode and PFM/PWM mode.

With the MODE/SYNC pin set to high, the TPSM8281x operates with pulse width modulation in continuous

conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP/FSET pin to

GND or by an external clock signal applied to the MODE/SYNC pin.

8.4.2 Power Save Mode Operation (PFM/PWM)

When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long

as the peak inductor current is above the PFM threshold of about 1.2A. When the peak inductor current drops

below the PFM threshold, the device starts to skip switching pulses.

In power save mode, the switching frequency decreases linearly with the load current to maintain high efficiency.

The linear behavior of the switching frequency in power save mode is shown in Figure 8-1.

TPSM82810, TPSM82813

SLUSDN6B – SEPTEMBER 2019 – REVISED JULY 2024

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