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S71PL129JC0 Datasheet(PDF) 117 Page - SPANSION |
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S71PL129JC0 Datasheet(HTML) 117 Page - SPANSION |
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117 / 153 page  October 28, 2005 S71PL129Jxx_00_A8 S71PL129JC0/S71PL129JB0/S71PL129JA0 115 Advance Informatio n Mode Register Update and Deep Sleep Timings Notes: 1. Minimum cycle time for writing register is equal to speed grade of product. Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M) Figure 42. Deep Sleep Mode - Entry/Exit Timings (for 32M and 16M) Item Symbol Min Max Unit Note Chip deselect to ZZ# low tCDZZ 5 ns ZZ# low to WE# low tZZWE 10 500 ns Write register cycle time tWC 70/85 ns 1 Chip enable to end of write tCW 70/85 ns 1 Address valid to end of write tAW 70/85 ns 1 Write recovery time tWR 0 ns Address setup time tAS 0 ns Write pulse width tWR 40 ns Deep Sleep Pulse Width tZZMIN 10 µs Deep Sleep Recovery tR 200 µs ZZ# tZZMIN tCDZZ tR CE# A4 ZZ# tWC tBW tAS CE# WE# tZZWE tAW tWP tWR tR tZZMIN LB#, UB# |
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