LTC2489CDEPBF datasheet(9/24 Pages) LINER

9 / 24 page

LTC2489

2489f

CONVERTER OPERATION

Converter Operation Cycle

The LTC2489 is a multichannel, low power, delta-sigma

analog-to-digital converter with a 2-wire, I2C interface.

Its operation is made up of four states (see Figure 1).

The converter operating cycle begins with the conver-

sion, followed by the sleep state and ends with the data

input/output cycle .

APPLICATIONS INFORMATION

Figure 1. State Transition Table

CONVERSION

SLEEP

2489 F01

YES

ACKNOWLEDGE

YES

STOP

OR READ

24 BITS

DATA OUTPUT/INPUT

POWER-ON RESET

DEFAULT INPUT CHANNEL:

IN+ = CH0, IN– = CH1

the LTC2489 is addressed for a read operation, the device

begins outputting the conversion result under the control

of the serial clock (SCL). There is no latency in the conver-

sion result. The data output is 24 bits long and contains a

16-bit plus sign conversion result. Data is updated on the

falling edges of SCL allowing the user to reliably latch data

on the rising edge of SCL. A new conversion is initiated

by a stop condition following a valid write operation or an

incomplete read operation. The conversion automatically

begins at the conclusion of a complete read cycle (all 24

bits read out of the device).

Ease of Use

The LTC2489 data output has no latency, ﬁlter settling

delay, or redundant data associated with the conversion

cycle. There is a one-to-one correspondence between the

conversion and the output data. Therefore, multiplexing

multiple analog inputs is straightforward. Each conversion,

immediately following a newly selected input is valid and

accurate to the full speciﬁcations of the device.

The LTC2489 automatically performs offset and full-scale

calibration every conversion cycle independent of the

input channel selected. This calibration is transparent

to the user and has no effect on the operation cycle de-

scribed above. The advantage of continuous calibration

is extreme stability of offset and full-scale readings with

respect to time, supply voltage variation, input channel,

and temperature drift.

Easy Drive Input Current Cancellation

The LTC2489 combines a high precision, delta-sigma ADC

with an automatic, differential, input current cancellation

front end. A proprietary front end passive sampling network

transparently removes the differential input current. This

enables external RC networks and high impedance sen-

sors to directly interface to the LTC2489 without external

ampliﬁers. The remaining common mode input current

is eliminated by either balancing the differential input im-

pedances or setting the common mode input equal to the

common mode reference (see the Automatic Differential

Input Current Cancellation section). This unique architec-

ture does not require on-chip buffers, thereby enabling

signals to swing beyond ground and VCC. Moreover, the

Initially, at power-up, the LTC2489 performs a conver-

sion. Once the conversion is complete, the device enters

the sleep state. In the sleep state, power consumption is

reduced by two orders of magnitude. The part remains in

the sleep state as long it is not addressed for a read/write

operation. The conversion result is held indeﬁnitely in a

static shift register while the part is in the sleep state.

The device will not acknowledge an external request dur-

ing the conversion state. After a conversion is ﬁnished,

the device is ready to accept a read/write request. Once

LTC2489CDEPBF Datasheet(PDF) 9 Page - Linear Technology

LTC2489CDEPBF Datasheet(HTML) 9 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL