 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LTM4686 Datasheet(PDF) 9 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
LTM4686 Datasheet(HTML) 9 Page - Analog Devices |
|
|
9 / 130 page  9 LTM4682 Rev. 0 For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V, RUNP = 12V, FREQUENCY_SWITCH = 575kHz and VOUTn commanded to 0.75V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD25_nn Regulator VVDD25nn Internal VDD25 Voltage 2.5 V ILIM VDD25 Current Limit VDD25_nn = GND, VIN_nn = INTVCC_nn = 4.5V 80 mA Oscillator and Phase-Locked Loop (PLL) fRANGE PLL SYNC Range Synchronized with Falling Edge of SYNC 250 1000 kHz fOSC Oscillator Frequency Accuracy Frequency Switch = 250kHz to 1000kHz (Note 14) l ±7.5 % VTH(SYNC_nn) SYNC Input Threshold (Note 14) VSYNC Falling VSYNC Rising 1 1.5 V V VOL(SYNC_nn) SYNC Low Output Voltage ILOAD = 3mA (Note 14) 0.2 0.4 V ILEAK(SYNC_nn) SYNC Leakage Current in Subordinate Mode 0V ≤ VSYNC_nn ≤ 3.6V ±5 µA θSYNC-θ0, -θ2 SYNC to Ch0, Ch2 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of SW0, SW2 MFR_PWM_CONFIG[2:0] = 0,2,3 MFR_PWM_CONFIG[2:0] = 5 MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0]= 4,6 0 60 90 120 Deg Deg Deg Deg θSYNC-θ1, -θ3 SYNC to Ch1, Ch3 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of SW1, SW3 MFR_PWM_CONFIG[2:0] = 3 MFR_PWM_CONFIG[2:0] = 0 MFR_PWM_CONFIG[2:0] = 2,4,5 MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0] = 6 120 180 240 270 300 Deg Deg Deg Deg Deg EEPROM Characteristics Endurance (Note 15) 0°C ≤ TJ ≤ 85°C During EEPROM Write Operations l 10,000 Cycles Retention (Note 15) TJ < 125°C l 10 Years Mass_Write Mass Write Operation Time STORE_USER_ALL, 0°C < TJ < 85°C During EEPROM Write Operation 440 4100 ms Leakage Current SDA_nn, SCL_nn, ALERT_nn, RUNn IOL Input Leakage Current OV ≤ VPIN ≤ 5.5V l ±5 µA Leakage Current FAULTn, PGOODn IGL Input Leakage Current OV ≤ VPIN ≤ 3.6V l ±2 µA Digital Inputs SCL_nn, SDA_nn, RUNn VIH Input High Threshold Voltage l 1.35 V VIL Input Low Threshold Voltage l 0.8 V VHYST Input Hysteresis SCL, SDA 0.08 V CPIN Input Capacitance 10 pF Digital Input WP_nn (Note 14) (Note 14) IPUWP Input Pull-Up Current WP 10 µA Open-Drain Outputs SCL_nn, SDA_nn, FAULTn, ALERT_nn, RUNn, SHARE_CLK_nn, PGOODn VOL Output Low Voltage ISINK = 3mA 0.4 V Digital Inputs SHARE_CLK_nn, WP_nn (Note 14) VIH Input High Threshold Voltage l 1.5 1.8 V VIL Input Low Threshold Voltage l 0.6 1 V |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
