AD9163BBCZ datasheet(3/126 Pages) AD

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Data Sheet

AD9163

Rev. D | Page 3 of 126

REVISION HISTORY

5/2019—Rev. C to Rev. D

Changes to INPUTS (SDIO, SCLK, CS, RESET, EX_ENABLE)

Parameters, Table 4 ...........................................................................6

Changes to Table 10 and Thermal Resistance Section ...............10

Change to Transport Layer Testing Section.................................46

Changes to Data Format Section...................................................50

Deleted Table 36; Renumbered Sequentially...............................55

Changes to Changing the NCO Frequency Section ...................55

Deleted Endnote 2, Table 36 ..........................................................56

Changes to Peak DAC Output Power Capability Section..........65

Change to Register 0x280, Table 41 ..............................................68

Changes to Table 43 ........................................................................69

Changes to Table 44 ........................................................................76

Updated Outline Dimensions......................................................126

7/2017—Rev. B to Rev. C

Changes to Table 44 ........................................................................74

Changes to Table 45 ......................................................................118

5/2017—Rev. A to Rev. B

Changes to Start-Up Sequence Section ........................................67

2/2017—Rev. 0 to Rev. A

Change to Endnote 1, Table 1..........................................................4

Added Temperature Sensor Parameter, Table 1............................4

Change to OUTPUT± to VNEG_N1P2 Parameter, Table 10......10

Changes to Figure 99 ......................................................................38

Changes to Link Delay Setup Example, With Known Delays

Section ..............................................................................................40

Changes to Link Delay Setup Example, Without Known Delays

Section ..............................................................................................41

Changes to Table 23 ........................................................................43

Changed 4× Six-Lane (L = 3, M = 2, F = 4, S = 3) to 4× Three-Lane

(L = 3, M = 2, F = 4, S = 3), Table 29 ............................................46

Added Datapath PRBS Section and Datapath PRBS

IRQ Section.......................................................................................56

Moved Figure 133............................................................................64

Added Temperature Sensor Section .............................................65

Changes to Equivalent DAC Output and Transfer Function

Section ..............................................................................................65

Changes to Output Stage Configuration Section and Figure 140

Caption .............................................................................................66

Added Register 0x132 Row to Register 0x135 Row, Table 44 ........70

Added Register 0x132 Row to Register 0x135 Row, Table 45 ........84

Change to Register 0x230...............................................................86

7/2016—Revision 0: Initial Version

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