AD9163BBCZ datasheet(4/126 Pages) AD

4 / 126 page

AD9163

Data Sheet

Rev. D | Page 4 of 126

SPECIFICATIONS

DC SPECIFICATIONS

VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =

DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, DAC output full-scale current (IOUTFS) = 40 mA, and TA = −40°C to

+85°C, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

RESOLUTION

Bit

DAC Update Rate

Minimum

1.5

GSPS

Maximum

VDDx1 = 1.3 V ± 2%2

6.4

GSPS

VDDx1 = 1.3 V ± 2%2, FIR853 2× interpolator enabled

12.8

GSPS

Adjusted4

VDDx1 = 1.3 V ± 2%2

1.0667

GSPS

ACCURACY

Integral Nonlinearity (INL)

±2.7

LSB

Differential Nonlinearity (DNL)

±1.7

LSB

ANALOG OUTPUTS

Gain Error (with Internal

Reference)

−1.7

Full-Scale Output Current

Minimum

RSET = 9.76 kΩ

7.37

8.57

Maximum

RSET = 9.76 kΩ

35.8

38.76

41.3

DAC CLOCK INPUT (CLK+, CLK−)

Differential Input Power

RLOAD = 90 Ω differential on chip

−20

+10

dBm

Common-Mode Voltage

AC-coupled

0.6

Input Impedance1

3 GSPS input clock

Ω

TEMPERATURE DRIFT

Gain

105

ppm/°C

Reference Voltage

ppm/°C

TEMPERATURE SENSOR

Accuracy

After single point calibration (see the Temperature Sensor section)

±5

REFERENCE

Internal Reference Voltage

1.19

ANALOG SUPPLY VOLTAGES

VDD25_DAC

2.375

2.5

2.625

VDD12A2

1.14

1.2

1.326

VDD12_CLK2

1.14

1.2

1.326

VNEG_N1P2

−1.26

−1.2

−1.14

DIGITAL SUPPLY VOLTAGES

DVDD

1.14

1.2

1.326

IOVDD3

1.71

2.5

3.465

SERDES SUPPLY VOLTAGES

VDD_1P2

1.14

1.2

1.326

VTT_1P2

Can connect to VDD_1P2

1.14

1.2

1.326

DVDD_1P2

1.14

1.2

1.326

PLL_LDO_VDD12

1.14

1.2

1.326

PLL_CLK_VDD12

Can connect to PLL_LDO_VDD12

1.14

1.2

1.326

SYNC_VDD_3P3

3.135

3.3

3.465

BIAS_VDD_1P2

Can connect to VDD_1P2

1.14

1.2

1.326

See the Clock Input section for more details.

For the lowest noise performance, use a separate power supply filter network for the VDD12_CLK and the VDD12A pins.

IOVDD can range from 1.8 V to 3.3 V, with ±5% tolerance.

The adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9163, the minimum interpolation factor is 6. Therefore, with

fDAC = 6 GSPS, fDAC adjusted = 1 GSPS. When FIR85 is enabled, which puts the device into 2× NRZ mode, fDAC = 2 × (DAC clock input frequency), and the minimum interpolation

increases to 12× (interpolation value). Thus, for the AD9163, with FIR85 enabled and DAC clock = 6 GSPS, fDAC = 12 GSPS, minimum interpolation = 12×, and the adjusted DAC

update rate = 1 GSPS.

AD9163BBCZ Datasheet(PDF) 4 Page - Analog Devices

AD9163BBCZ Datasheet(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL