AD9163BBCZ datasheet(97/126 Pages) AD

97 / 126 page

Data Sheet

AD9163

Rev. D | Page 97 of 126

Hex.

Addr. Name

Bits Bit Name

Settings

Description

Reset Access

0x32D SHORT_TPL_TEST_1

[7:0] SHORT_TPL_REF_SP_LSB

Short transport layer reference

sample LSB. This is the lower eight

bits of expected DAC sample. It is

used to compare with the received

DAC sample at the output of

JESD204B Rx.

0x0

R/W

0x32E SHORT_TPL_TEST_2

[7:0] SHORT_TPL_REF_SP_MSB

Short transport layer test reference

sample MSB. This is the upper eight

bits of expected DAC sample. It is

used to compare with the received

sample at JESD204B Rx output.

0x0

R/W

0x32F SHORT_TPL_TEST_3

[7:1] RESERVED

Reserved.

0x0

SHORT_TPL_FAIL

Short transport layer test fail. This bit

shows if the selected DAC sample

matches the reference sample. If

they match, the test passes;

otherwise, the test fails.

0x0

0 Test pass.

1 Test fail.

0x334 JESD_BIT_INVERSE_CTRL

[7:0] JESD_BIT_INVERSE

Each bit of this byte inverses the

JESD204B deserialized data from

one specific JESD204B Rx PHY. The

bit order matches the logical lane

order. For example, Bit 0 controls

Lane 0, Bit 1 controls Lane 1.

0x0

R/W

0x400 DID_REG

[7:0] DID_RD

Received ILAS configuration on

Lane 0. DID is the device ID number.

Link information received on Lane 0

as specified in Section 8.3 of

JESD204B.

0x0

0x401 BID_REG

[7:0] BID_RD

Received ILAS configuration on

Lane 0. BID is the bank ID, extension

to DID. Link information received on

Lane 0 as specified in Section 8.3 of

JESD204B.

0x0

0x402 LID0_REG

RESERVED

Reserved.

0x0

ADJDIR_RD

Received ILAS configuration on

Lane 0. ADJDIR is the direction to

adjust the DAC LMFC. Link

information received on Lane 0 as

specified in Section 8.3 of JESD204B.

0x0

PHADJ_RD

Received ILAS configuration on

Lane 0. PHADJ is the phase

adjustment request to DAC. Link

information received on Lane 0 as

specified in Section 8.3 of JESD204B.

0x0

[4:0] LL_LID0

Received ILAS LID configuration

on Lane 0. LID0 is the lane

identification for Lane 0. Link

information received on Lane 0 as

specified in Section 8.3 of

JESD204B.

0x0

0x403 SCR_L_REG

SCR_RD

Received ILAS configuration on

Lane 0. SCR is the Tx scrambling

status. Link information received

on Lane 0 as specified in

Section 8.3 of JESD204B.

0x0

0 Scrambling is disabled.

1 Scrambling is enabled.

[6:5] RESERVED

Reserved.

0x0

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