A Product Line of

Diodes Incorporated

PI6CB332000

9

June 2024

© 2024 Copyright Diodes Incorporated. All Rights Reserved.

PI6CB332000

Document Number DS41283 Rev 7-2

www.diodes.com

HCSL Input Characteristics(1)

Temperature = TA. Supply voltages per normal operation conditions. See test circuits for the load conditions.

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Units

fIN

Input Frequency

—

1

100

200

MHz

VIHDIF

Differential Input High Voltage(3) IN+, IN-, single-ended measure-

ment

330

—

1150

mV

VILDIF

Differential Input Low Voltage(3)

IN+, IN-, single-ended measure-

ment

-300

0

300

mV

VSWING

Differential Input Swing Voltage

Peak-to-peak value (VIHDIF -

VILDIF)

200

—

—

mV

VCOM

Common Mode Voltage

—

0

—

900

mV

tRF

Differential Input Slew Rate(2)

—

0.7

—

—

V/ns

IIN

Differential Input Leakage Cur-

rent

VIN = VDD, VIN = GND

-5

—

5

µA

tDC

Differential Input Duty Cycle

Measured differentially

45

—

55

%

tjc-c

Differential Input Cycle-to-Cycle

Jitter

Measured differentially

—

—

125

ps

Note:

1. Guaranteed by design and characterization—not 100% tested in production.

2. Slew rate measured through ±75mV window centered around differential zero.

3. The device can be driven by a single-ended clock by driving the true clock and biasing the complement clock input to the Vbias, where Vbias is (VIH-VIL)/2.

Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions

Symbol

Parameters

Condition

Min.

Typ.

Max.

Units

VOH

Output Voltage High(1)

—

225

—

270

mV

VOL

Output Voltage Low(1)

10

0

150

mV

VOMAX

Output Voltage Maximum (Over-

shoot)(1)

—

—

—

VOH +

75mV

mV

VOMIN

Output Voltage Minimum (Un-

dershoot)(1)

VOL +

75mV

—

—

mV

Vcross abso-

lute

Absolute Crossing Point Volt-

age(1,2)

—

130

—

200

mV

Vcross rela-

tive

Relative Crossing Point Volt-

age(1,2)

—

—

—

35

mV

DC Distor-

tion

Duty Cycle Distortion(3,4)

—

-1

—

1

%

Note:

1. At default SMBUS amplitude settings.

2. Guaranteed by design and characterization—not 100% tested in production.

3. Measured from differential waveform.

4. Duty cycle distortion is the difference in duty cycle between the out and input clock when the device is operated in the PLL bypass mode.

HCSL Output DC Characteristics