TDA8752HSLASH6 datasheet(11/36 Pages) PHILIPS

11 / 36 page

1999 Mar 09

Philips Semiconductors

Product speciﬁcation

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

FUNCTIONAL DESCRIPTION

This triple high-speed 8-bit ADC is designed to convert

RGB signals, from a PC or work station, into data used by

a LCD driver (pixel clock up to 200 MHz, using 2 ICs).

IC analog video inputs

The video inputs are internally DC polarized. These inputs

are AC coupled externally.

Clamps

Three independent parallel clamping circuits are used to

clamp the video input signals on the black level and to

control the brightness level. The clamping code is

programmable between code

−63.5 and +64 in steps of

⁄2LSB. The programming of the clamp value is achieved

via an 8-bit DAC. Each clamp must be able to correct an

offset from

±0.1 V to ±10 mV within 300 ns, and correct the

total offset in 10 lines.

The clamps are controlled by an external TTL positive

going pulse (pin CLP). The drop of the video signal is

<1 LSB.

Normally, the circuit operates with a 0 code clamp,

corresponding to the 0 ADC code. This clamp code can be

changed from

−63.5 to +64 as represented in Fig.7,

in steps of 1

⁄2LSB. The digitized video signal is always

between code 0 and code 255 of the ADC.

Variable gain ampliﬁer

Three independent variable gain amplifiers are used to

provide, to each channel, a full-scale input range signal to

the 8-bit ADC. The gain adjustment range is designed so

that, for an input range varying from 0.4 to 1.2 V (p-p), the

output signal corresponds to the ADC full-scale input of

1 V (p-p).

To ensure that the gain does not vary over the whole

operating temperature range, an external reference of

+2.5 V DC, (Vref with a 100 ppm/°C maximum variation)

supplied externally, is used to calibrate the gain at the

beginning of each video line before the clamp pulse using

the following principle.

A differential of 0.156 V (p-p) (1

⁄16Vref) reference signal is

generated internally from the reference voltage (Vref).

During the synchronization part of the video line, the

multiplexer, controlled by the TTL synchronization signal

(HSYNCI, coming from HSYNC; see Fig.1) with a width

equal to one of the video synchronization signals

(e.g. signal coming from a synchronization separator), is

switched between the two amplifiers.

The output of the multiplexer is either the normal video

signal or the 0.156 V reference signal (during HSYNC).

The corresponding ADC outputs are then compared to a

pre-set value loaded in a register. Depending on the result

of the comparison, the gain of the variable gain amplifiers

is adjusted (coarse gain control; see Figs 2 and 8).

The three 7-bit registers receive data via a serial interface

to enable the gain to be programmed.

The pre-set value loaded in the 7-bit register is chosen

between approximately 67 codes to ensure the full-scale

input range (see Fig.8). A contrast control can be achieved

using these registers. In this case care should be taken to

stay within the allowed code range (32 to 99).

A fine correction using three 5-bit DACs, also controlled via

the serial interface, is used to finely tune the gain of the

three channels (fine gain control; see Figs 2 and 9) and to

compensate the channel-to-channel gain mismatch.

With a full scale ADC input, the resolution of the fine

⁄2LSB peak-to-peak variation.

To use these gain controls correctly, it is recommended to

fix the coarse gain (to have a full-scale ADC input signal)

to within 4LSB and then adjust it with the fine gain.

The gain is adjusted during HSYNC. During this time the

output signal is not related to the amplified input signal.

The outputs, when the coarse gain system is stable, is

related to the programmed coarse code (see Fig.8).

ADCs

The ADCs are 8-bit with a maximum clock frequency of

100 Msps. The ADCs input range is 1 V (p-p) full-scale.

One out of range bit exists per channel (ROR, GOR and

BOR). It will be at logic 1 when the signal is out of range of

the full scale of the ADCs.

Pipeline delay in the ADCs is 1 clock cycle from sampling

to data output.

The ADCs reference ladders regulators are integrated.

ADC outputs

ADC outputs are straight binary. An output enable pin

(OE; active LOW) enables the output status between

active and high-impedance (OE = HIGH) to be switched;

it is recommended to load the outputs with a 10 pF

capacitive load. The timing must be checked very carefully

if the capacitive load is more than 10 pF.

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