TDA8752HSLASH6 datasheet(12/36 Pages) PHILIPS

12 / 36 page

1999 Mar 09

Philips Semiconductors

Product speciﬁcation

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

Phase-locked loop

The ADCs are clocked either by an internal PLL locked to

the CKREF clock, (all of the PLL is on-chip except the loop

filter capacitance) or an external clock, CKEXT. Selection

is performed via the serial interface bus.

The reference clock (CKREF) range is between

15 and 280 kHz. Consequently, the VCO minimum

frequency is 12 MHz and the maximum frequency

100 MHz for the TDA8752/8 and 60 MHz for the

TDA8752/6. The gain of the VCO part can be controlled via

the serial interface, depending on the frequency range to

which the PLL is locked.

To increase the bandwidth of the PLL, the charge pump

current, controlled by the serial interface, must also be

increased. The relationship between the frequency and

the current is given by the following equation:

Where:

fn = the natural PLL frequency

KO = the VCO gain

N = the division number

Cz and CP = capacitors of the PLL filter.

The other PLL equation is as follows:

-------

O IP

(

P ) N

-----------------------------------

Where:

fz = loop filter zero frequency

R = the chosen resistance for the filter

ξ = the damping factor.

Different resistances for the filter can be programmed via

the serial interface. To have better performances, the PLL

parameters should be chosen so that:

fn/fref ≅ 0.05

ξ≅ 1.5.

It is possible to control (independently) the phase of the

ADC clock and the phase of an additional clock output

(which could be used to drive a second TDA8752).

For this, two serial interface-controlled digital phase-shift

controllers are included (controlled by 5-bit registers,

phase shift controller steps are 11.25

° each on the whole

PLL frequency range).

CKREF is resynchronized, by the synchro block, on the

CKAO clock. The output is CKREFO (LOW during 8 clock

periods). CKAO is the clock at the output of the phase

selector A. This clock can be used as the clocks for CKBO

and CKADCO. The timing is given in Fig.5.

π R

------------------------------ and

---

----







tCKAO =tCLK(buffer) +tphase selector (tCLK(buffer) = 10 ns and tphase selector =

× TCLK(pixel)).

tCKREFO = either tCKAO if phase A ≥01000 or tCKAO +TCLK(pixel) if phase A <01000.

phase selector

-------------------------------

Fig.5 Timing.

andbook, full pagewidth

tCKAO

tCKREFO

MBK773

CKREF

CKAO

CKREFO

TDA8752H/6 Datasheet(PDF) 12 Page - NXP Semiconductors

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