25LC1024-ESLASHMF datasheet(16/30 Pages) MICROCHIP

16 / 30 page

25AA1024/25LC1024

DS21836D-page 16

Preliminary

2.10

CHIP ERASE

The Chip Erase function will erase all bits (FFh) in the

array. A Write Enable (WREN) instruction must be given

prior to executing a Chip Erase. This is done by setting

CS low and then clocking out the proper instruction

into the 25XX1024. After all eight bits of the instruction

are transmitted, the CS must be brought high to set

the write enable latch.

The Chip Erase function is entered by driving the CS

low, followed by the instruction code (Figure 2-10)

onto the SI line.

The CS pin must be driven high after the eighth bit of

the instruction code has been given or the Chip Erase

function will not be executed. Once the CS pin is

driven high, the self-timed Chip Erase function begins.

While the device is executing the Chip Erase function

the WIP bit in the STATUS register can be read to

determine when the Chip Erase function is complete.

The Chip Erase function is ignored if either of the

Block Protect bits (BP0, BP1) are not 0, meaning ¼,

½, or all of the array is protected.

FIGURE 2-10:

CHIP ERASE SEQUENCE

SCK

High-Impedance

25LC1024-E/MF Datasheet(PDF) 16 Page - Microchip Technology