FALXT972MCCA4 datasheet(65/92 Pages) INTEL

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Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

7.2

Timing Diagrams

Figure 22. Intel® LXT972M Transceiver 100BASE-TX Receive Timing

Table 30. Intel® LXT972M Transceiver 100BASE-TX Receive Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

RXD[3:0], RX_DV, RX_ER

3 setup to

RX_CLK High

–

RXD[3:0], RX_DV, RX_ER hold

from RX_CLK High

–

CRS asserted to RXD[3:0], RX_DV

–

Receive start of “J” to CRS asserted

–

Receive start of “T” to CRS de-asserted

–

Receive start of “J” to COL asserted

–

Receive start of “T” to COL de-asserted

–

1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production

testing.

2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit

rate. 100BASE-T bit time = 10

-8 s or 10 ns.

3. RX_ER is not shown in the figure.

0 ns

250 ns

CRS

RX_DV

RXD[3:0]

RX_CLK

COL

TPI

B3492-03

Note: Timing diagram depicts 4B mode.

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