FALXT972MCCA4 datasheet(55/92 Pages) INTEL

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Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

5.10

Boundary Scan (JTAG 1149.1) Functions

The LXT972M Transceiver includes a IEEE 1149.1 boundary scan test port for board level testing.

All digital input, output, and input/output pins are accessible.

Note:

For the related BSDL file, contact your local sales office or access the Intel website

(www.intel.com).

5.10.1

Boundary Scan Interface

The boundary scan interface consists of five pins (TMS, TDI, TDO, TRST_L, and TCK). It

includes a state machine, data register array, and instruction register. The TMS and TDI pins are

pulled up internally. TCK is pulled down internally. TDO does not have an internal pull-up or pull-

down.

5.10.2

State Machine

The TAP controller is a state machine, with 16 states driven by the TCK and TMS pins. Upon reset,

the TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are

high for five TCK periods.

5.10.3

Instruction Register

After the state machine resets, the IDCODE instruction is always invoked. The decode logic

ensures the correct data flow to the Data registers according to the current instruction.

Table 16 lists valid JTAG instructions for the LXT972M Transceiver.

Table 16. Valid JTAG Instructions

Name

Code

Description

Mode

Data Register

EXTEST

1111 1111 1110 1000

External Test

Test

BSR

IDCODE

1111 1111 1111 1110

ID Code Inspection

Normal

ID REG

SAMPLE

1111 1111 1111 1000

Sample Boundary

Normal

BSR

HIGHZ

1111 1111 1100 1111

Force Float

Normal

Bypass

CLAMP

1111 1111 1110 1111

Control Boundary to 1/0

Test

Bypass

BYPASS

1111 1111 1111 1111

Bypass Scan

Normal

Bypass

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