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FALXT972MCCA4 Datasheet(PDF) 37 Page - Intel Corporation

Part # FALXT972MCCA4
Description  Single-Port 10/100 Mbps PHY Transceiver
PDF  92 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

FALXT972MCCA4 Datasheet(HTML) 37 Page - Intel Corporation

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Intel
® LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
37
Document Number: 302875-005
Revision Date: 27-Oct-2005
5.6.1
MII Clocks
The LXT972M Transceiver is the master clock source for data transmission, and it supplies both
MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link
conditions.
• When the link is operating at 100 Mbps, the clocks are set to 25 MHz.
• When the link is operating at 10 Mbps, the clocks are set to 2.5 MHz.
Figure 7 through Figure 9 show the clock cycles for each mode.
Note:
The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The
LXT972M Transceiver samples these signals on the rising edge of TX_CLK.
Figure 7. Clocking for 10BASE-T
Figure 8. Clocking for 100BASE-X
RX_CLK
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
TX_CLK
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
Constant 25 MHz
XI
B3390-01
RX_CLK
2.5 MHz during auto-negotiation
TX_CLK
Constant 25 MHz
XI
25 MHz once 100BASE-X
Link Established
2.5 MHz during auto-negotiation
25 MHz once 100BASE-X
Link Established
B3391-01



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