PIC16CR74ESLASHP datasheet(77/172 Pages) MICROCHIP

77 / 172 page

DS21993C-page 75

PIC16CR7X

FIGURE 10-3:

ASYNCHRONOUS MASTER TRANSMISSION (BACK-TO-BACK)

TABLE 10-5:

REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

10.2.2

USART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 10-4.

The data is received on the RC7/RX/DT pin and drives

the data recovery block. The data recovery block is

actually a high-speed shifter operating at x16 times the

baud rate, whereas the main receive serial shifter

operates at the bit rate, or at FOSC.

Once Asynchronous mode is selected, reception is

enabled by setting bit CREN (RCSTA<4>).

The heart of the receiver is the Receive (serial) Shift

received data in the RSR is transferred to the RCREG

bit RCIF (PIR1<5>) is set. The actual interrupt can be

enabled/disabled by setting/clearing enable bit RCIE

(PIE1<5>). Flag bit RCIF is a read-only bit which is

cleared by the hardware. It is cleared when the RCREG

double buffered register (i.e., it is a two-deep FIFO). It

is possible for two bytes of data to be received and

transferred to the RCREG FIFO and a third byte to

begin shifting to the RSR register. On the detection of

the Stop bit of the third byte, if the RCREG register is

still full, the overrun error bit OERR (RCSTA<1>) will be

set. The word in the RSR will be lost. The RCREG

the FIFO. Overrun bit OERR has to be cleared in soft-

ware. This is done by resetting the receive logic (CREN

is cleared and then set). If bit OERR is set, transfers

from the RSR register to the RCREG register are inhib-

ited and no further data will be received, therefore, it is

essential to clear error bit OERR if it is set. Framing

error bit FERR (RCSTA<2>) is set if a Stop bit is

detected as clear. Bit FERR and the 9th receive bit are

buffered the same way as the receive data. Reading

the RCREG will load bits RX9D and FERR with new

values, therefore, it is essential for the user to read the

RCSTA register before reading RCREG register, in

order not to lose the old FERR and RX9D information.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

Resets

0Bh, 8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D

0000 -00x

19h

TXREG

USART Transmit Data Register

0000 0000

8Ch

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

99h

SPBRG

Baud Rate Generator Register

0000 0000

Legend:

= unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

Note

Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.

Transmit Shift Reg.

Write to TXREG

BRG Output

(Shift Clock)

RC6/TX/CK (pin)

TXIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Word 2

Word 1

Word 2

Start bit

Stop bit

Start bit

Transmit Shift Reg.

Word 1

Word 2

bit 0

bit 1

bit 7/8

bit 0

Note: This timing diagram shows two consecutive transmissions.

PIC16CR74E/P Datasheet(PDF) 77 Page - Microchip Technology

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