PIC16CR74ESLASHP datasheet(139/172 Pages) MICROCHIP

139 / 172 page

DS21993C-page 137

PIC16CR7X

FIGURE 15-18:

A/D CONVERSION TIMING

TABLE 15-13: A/D CONVERSION REQUIREMENTS

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

130

TAD

A/D clock period

PIC16CR7X

1.6

—

μsTOSC based, VREF ≥ 3.0V

PIC16CR7X

2.0

—

μsTOSC based,

2.0V

≤ VREF ≤ 5.5V

PIC16CR7X

2.0

4.0

6.0

μs A/D RC mode

PIC16CR7X

3.0

6.0

9.0

μs A/D RC mode

131

TCNV Conversion time (not including

S/H time) (Note 1)

9—

TAD

132

TACQ Acquisition time

—

μs The minimum time is the

amplifier settling time. This

may be used if the “new” input

voltage has not changed by

more than 1 LSb (i.e.,

20.0 mV @ 5.12V) from the

last sampled voltage (as

stated on CHOLD).

134

TGO

Q4 to A/D clock start

—

TOSC/2

—

If the A/D clock source is

selected as RC, a time of TCY

is added before the A/D clock

starts. This allows the SLEEP

instruction to be executed.

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1:

ADRES register may be read on the following TCY cycle.

See Section 11.1 “A/D Acquisition Requirements” for minimum conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

(TOSC/2)(1)

432

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction

to be executed.

1 TCY

134

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