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PIC12F635-I/ST Datasheet(PDF) 177 Page - Microchip Technology |
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PIC12F635-I/ST Datasheet(HTML) 177 Page - Microchip Technology |
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177 / 234 page  © 2007 Microchip Technology Inc. DS41232D-page 175 PIC12F635/PIC16F636/639 15.7 DC Characteristics: PIC16F639-I (Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Supply Voltage 2.0V ≤ VDD ≤ 3.6V Param No. Sym Characteristic Min Typ† Max Units Conditions VIL Input Low Voltage I/O ports: D030A with TTL buffer VSS — 0.15 VDD V D031 with Schmitt Trigger buffer VSS —0.2 VDD V D032 MCLR, OSC1 (RC mode) VSS —0.2 VDD V D033 OSC1 (XT and LP modes)(1) VSS —0.3 V D033A OSC1 (HS mode)(1) VSS —0.3 VDD V D034 Digital Input Low Voltage VSS —0.3 VDD V Analog Front-End section VIH Input High Voltage I/O ports: D040 with TTL buffer D040A (0.25 VDD + 0.8) — VDD V D041 with Schmitt Trigger buffer 0.8 VDD —VDD V D042 MCLR 0.8 VDD —VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V (Note 1) D043A OSC1 (HS mode) 0.7 VDD —VDD V (Note 1) D043B OSC1 (RC mode) 0.9 VDD —VDD V Digital Input High Voltage Analog Front-End section D044 SCLK, CS, SDIO for Analog Front-End (AFE) 0.8 VDD —VDD V IIL Input Leakage Current(2) D060 I/O ports — ± 0.1 ± 1 μAVSS ≤ VPIN ≤ VDD, Pin at high-impedance D060A Analog inputs — ± 0.1 ± 1 μAVSS ≤ VPIN ≤ VDD D060B VREF — ± 0.1 ± 1 μAVSS ≤ VPIN ≤ VDD D061 MCLR(3) — ± 0.1 ± 5 μAVSS ≤ VPIN ≤ VDD D063 OSC1 — ± 0.1 ± 5 μAVSS ≤ VPIN ≤ VDD, XT, HS and LP oscillator configuration Digital Input Leakage Current(2) VDD = 3.6V, Analog Front-End section D064 SDI for Analog Front-End (AFE) — — ± 1 μAVSS ≤ VPIN ≤ VDD D064A SCLK, CS for Analog Front-End (AFE) —— ± 1 μAVPIN ≤ VDD D070 IPUR PORTA Weak Pull-up Current 50* 250 400 μAVDD = 3.6V, VPIN = VSS D071 IPDR PORTA Weak Pull-down Current 50 250 400 μAVDD = 3.6V, VPIN = VDD VOL Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 3.6V (Ind.) D083 OSC2/CLKOUT (RC mode) — — 0.6 V IOL = 1.6 mA, VDD = 3.6V (Ind.) IOL = 1.2 mA, VDD = 3.6V (Ext.) Digital Output Low Voltage Analog Front-End section D084 ALERT, LFDATA/SDIO for Analog Front-End (AFE) —— VSS + 0.4 VIOL = 1.0 mA, VDD = 2.0V * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 9.4.1 “Using the Data EEPROM” for additional information |
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