CDB4397 datasheet(14/34 Pages) CIRRUS

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CS4397

DS333F1

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25 °C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF)

Notes: 12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

13. Data must be held for sufficient time to bridge the transition time of CCLK.

14. For FSCK < 1 MHz

Parameter

Symbol

Min

Max

Unit

SPI Mode

CCLK Clock Frequency

fsclk

-6

MHz

RST Rising Edge to CS Falling

tsrs

500

CCLK Edge to CS Falling

(Note 12)

tspi

500

CS High Time Between Transmissions

tcsh

1.0

µs

CS Falling to CCLK Edge

tcss

CCLK Low Time

tscl

CCLK High Time

tsch

CDIN to CCLK Rising Setup Time

tdsu

CCLK Rising to DATA Hold Time

(Note 13)

tdh

Rise Time of CCLK and CDIN

(Note 14)

tr2

100

Fall Time of CCLK and CDIN

(Note 14)

tf2

100

CCLK Falling to CDOUT valid

tov

t r2

t f2

t dsu t dh

t sch

t scl

CCLK

t css

t csh

t spi

t srs

RST

t ov

CDIN

CDOUT

Figure 5. SPI Control Port Timing

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