6.4

VBO UVLO protection

Dedicated undervoltage protection is available on each bootstrap section between BOOTx and OUTx supply pins.

In order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on

threshold.

When the VBO voltage goes below the VBOthOFF threshold, the HVG output of the corresponding bootstrap section

is switched off. When the VBO voltage reaches the VBOthON threshold, the device returns to normal operation and

the output remains off up to the next input pin transition that requests HVG to turn on.

Figure 13. VBO power-ON and UVLO timing

VBO

VCC

0 V

0 V

FAULT

HVG-OUT

HIN

0 V

0 V

VBO CHARGE

0V

VCCthON

VCCthOFF

VBOthON

VBOthOFF

Vil

Vih

6.5

Comparator and Smart shutdown

The PWD5T60 integrates a comparator committed to the fault protection function, thanks to the SmartShutDown

(SmartSD) circuit.

The SmartSD architecture allows immediate turn-off of the gate driver outputs in the case of overload or

overcurrent condition, by minimizing the propagation delay between the fault detection event and the actual

output switch-off. In fact, the time delay between the fault detection and the output turn-off is not dependent on the

value of the external components connected to the OD pin, which are only used to set the duration of disable time

after the fault.

This provides the possibility to increase the duration of the output disable time after the fault event up to very

large values without increasing the delay time of the protection. The duration of the disable time is determined by

the values of the external capacitor COD and of the optional pull-up resistor connected to the OD pin.

The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting

input is available on the CIN pin. The comparator's CIN input can be connected to an external shunt resistor in

order to implement a fast and simple overcurrent protection function. The output signal of the comparator is

filtered from glitches shorter than tFCIN and then fed to the SmartSD logic.

If the impulse on the CIN pin is higher than VREF and wider than tFCIN, the SmartSD logic is triggered and

immediately sets all of the driver outputs to low-level (OFF).

At the same time, FAULT is forced low to signal the event (for example to an MCU input) and OD starts to

discharge the external COD capacitor used to set the duration of the output disable time of the fault event.

The FAULT pin is released and driver outputs restart following the input pins as soon as the output disable time

expires.

The overall disable time is composed of two phases:

•

The OD unlatch time (t1 in Figure 14), which is the time required to discharge the COD capacitor down to

the VSSDl threshold. The discharge starts as soon as the SSD comparator is triggered.

PWD5T60

Functional description

DS14558 - Rev 2

page 14/27