List of figures

Figure 1.

PWD5T60 block diagram ............................................................. 2

Figure 2.

PWD5T60 pin connection ............................................................ 3

Figure 3.

Switching time definition ............................................................ 10

Figure 4.

Normalized gate threshold voltage vs temperature .......................................... 10

Figure 5.

Normalized drain-source breakdown voltage vs. temperature ................................... 10

Figure 6.

Static drain-source on-resistance ...................................................... 11

Figure 7.

Normalized on-resistance vs temperature ................................................ 11

Figure 8.

Transfer characteristics ............................................................. 11

Figure 9.

Output characteristics .............................................................. 11

Figure 10.

Static source-drain diode forward characteristics............................................ 11

Figure 11.

VCC power ON and UVLO, LVG timing .................................................. 13

Figure 12.

VCC power ON and UVLO, HVG timing .................................................. 13

Figure 13.

VBO power-ON and UVLO timing ...................................................... 14

Figure 14.

Smart shutdown timing waveforms ..................................................... 16

Figure 15.

Typical application 3-phase single-shunt ................................................. 17

Figure 16.

Package outline .................................................................. 20

Figure 17.

Suggested footprint (top view) ........................................................ 21

PWD5T60

List of figures

DS14558 - Rev 2

page 26/27