PM3351-SW datasheet(48/268 Pages) PMC

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PM3351 ELAN 1X100

DATA SHEET

PMC-970113

ISSUE 3

SINGLE PORT FAST ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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A series of two unidirectional buffer FIFOs for receiving data from the MII media:

the first is a 32-deep nibble-wide FIFO that receives framed nibbles from the MII

receive channel pins; the second is the primary 64 byte receive FIFO that

assembles the nibbles into 32-bit data words and buffers them prior to transfer

to the external SRAM. Additional control logic is provided to strip off the

preamble and Start Frame Delimiter (SFD) from the receive data, to assemble

the framed data nibbles into octets, and to perform clock synchronization

between the MII receive clock and the internal system clock. The assembled

and buffered data words are then passed to the DMA Controller, which in turn

writes them out to local memory.

Note that the MAC interface unit can begin receiving the next incoming frame

while the DMA is still servicing the previous frame; control information is inserted

into the FIFOs to ensure that the two frames are properly separated before

transfer to memory.

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A 2048-byte transmit FIFO is provided to buffer transmit data received from

other ELAN devices over the PCI expansion bus interface prior to transmission

on the MAC transmit channel. This FIFO is large enough to hold more than one

maximum sized frame of 1518 bytes (plus an additional 512 bytes of the next

frame), or up to 32 minimum sized (64-byte) frames, allowing frames to be

stacked back-to-back for continuous transmission in the presence of PCI bus

latencies.

Frame transmission on the MII port only starts if an entire frame is present in the

transmit FIFO, and the Switch Processor has indicated that the frame is to be

transmitted. During transmission, data octets are read from the transmit FIFO

by the transmit MAC interface logic, synchronized to the MII transmit clock, and

then output on the MII transmit data nibble pins. Additional logic in the transmit

interface implements the lower-level frame transmission process described in

the 802.3 specification (preamble and SFD insertion, interframe gap timing,

collision detection and carrier deference for half-duplex, etc.).

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Control/status registers and logic that allows the Switch Processor to control the

MAC port and the attached PHY devices, and also to monitor status. The

control/status registers contain the timers required for the CSMA/CD algorithm.

MAC transmit sequence

During transmission, 8-bit data octets to be transmitted are passed from the transmit

FIFO to the link transmit interface where they are synchronized to the MII transmit clock

(TX_CLK). After any required deference or interframe gap time, the MII framing signal

TX_EN is asserted and the preamble and SFD are sent on the TXD[3:0] pins. After the

SFD, the data octets comprising the Ethernet frame header and payload are

disassembled into nibbles, which are then transmitted on the TXD[3:0] pins, followed

PM3351-SW Datasheet(PDF) 48 Page - PMC-Sierra, Inc

PM3351-SW Datasheet(HTML) 48 Page - PMC-Sierra, Inc

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